mips-protos.h (mips_output_sync): Declare.

gcc/
	* config/mips/mips-protos.h (mips_output_sync): Declare.
	(mips_sync_loop_insns): Likewise.
	(mips_output_sync_loop): Replace first two parameters with an rtx.
	* config/mips/mips.c (mips_multi_member): New structure.
	(mips_multi_members): New variable.
	(mips_multi_start): New function.
	(mips_multi_add): Likewise.
	(mips_multi_add_insn): Likewise.
	(mips_multi_add_label): Likewise.
	(mips_multi_last_index): Likewise.
	(mips_multi_copy_insn): Likewise.
	(mips_multi_set_operand): Likewise.
	(mips_multi_write): Likewise.
	(mips_print_operand_punctuation): Remove '%|' and '%-'.
	(mips_init_print_operand_punct): Update accordingly.
	(mips_start_ll_sc_sync_block): New function.
	(mips_end_ll_sc_sync_block): Likewise.
	(mips_output_sync): Likewise.
	(mips_sync_insn1_template): Likewise.
	(mips_sync_insn2_template): Likewise.
	(mips_get_sync_operand): Likewise.
	(mips_process_sync_loop): Likewise.
	(mips_output_sync_loop): Use mips_process_sync_loop.
	(mips_sync_loop_insns): New function.
	* config/mips/mips.h (MIPS_COMPARE_AND_SWAP): Delete.
	(MIPS_COMPARE_AND_SWAP_12): Likewise.
	(MIPS_COMPARE_AND_SWAP_12_ZERO_OP): Likewise.
	(MIPS_COMPARE_AND_SWAP_12_NONZERO_OP): Likewise.
	(MIPS_SYNC_OP, MIPS_SYNC_OP_12): Likewise.
	(MIPS_SYNC_OP_12_AND, MIPS_SYNC_OP_12_XOR): Likewise.
	(MIPS_SYNC_OLD_OP_12): Likewise.
	(MIPS_SYNC_OLD_OP_12_AND, MIPS_SYNC_OLD_OP_12_XOR): Likewise.
	(MIPS_SYNC_NEW_OP_12): Likewise.
	(MIPS_SYNC_NEW_OP_12_AND, MIPS_SYNC_NEW_OP_12_XOR): Likewise.
	(MIPS_SYNC_OLD_OP, MIPS_SYNC_NEW_OP): Likewise.
	(MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND): Likewise.
	(MIPS_SYNC_EXCHANGE, MIPS_SYNC_EXCHANGE_12): Likewise.
	(MIPS_SYNC_EXCHANGE_12_ZERO_OP): Likewise.
	(MIPS_SYNC_EXCHANGE_12_NONZER_OP): Likewise.
	* config/mips/mips.md (sync_mem): New attribute.
	(sync_oldval, sync_newval, sync_inclusive_mask): Likewise.
	(sync_exclusive_mask, sync_required_oldval): Likewise.
	(sync_insn1_op2, sync_insn1, sync_insn2): Likewise.
	(sync_release_barrier): Likewise.
	(length): Handle sync loops.
	(sync): Use mips_output_sync.
	* config/mips/sync.md (*memory_barrier): Use mips_output_sync.
	(sync_compare_and_swap<mode>): Set the new sync_* attributes
	and use mips_output_sync_loop.
	(compare_and_swap_12, sync_add<mode>, sync_<optab>_12): Likewise.
	(sync_old_<optab>_12, sync_new_<optab>_12, sync_nand_12): Likewise.
	(sync_old_nand_12, sync_new_nand_12, sync_sub<mode>): Likewise.
	(sync_old_add<mode>, sync_old_sub<mode>): Likewise.
	(sync_new_add<mode>, sync_new_sub<mode>): Likewise.
	(sync_<optab><mode>, sync_old_<optab><mode>): Likewise.
	(sync_new_<optab><mode>, sync_nand<mode>): Likewise.
	(sync_old_nand<mode>, sync_new_nand<mode>): Likewise.
	(sync_lock_test_and_set<mode>, test_and_set_12): Likewise.

From-SVN: r151128

1 files changed, 152 insertions, 169 deletions

diff --git a/gcc/config/mips/sync.md b/gcc/config/mips/sync.md
index affb3fa..e28f56c 100644
--- a/gcc/config/mips/sync.md
+++ b/gcc/config/mips/sync.md
@@ -40,7 +40,7 @@
   [(set (match_operand:BLK 0 "" "")
 	(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
   "GENERATE_SYNC"
-  "%|sync%-")
+  { return mips_output_sync (); })
 
 (define_insn "sync_compare_and_swap<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
@@ -50,15 +50,12 @@
 			      (match_operand:GPR 3 "arith_operand" "I,d")]
 	 UNSPEC_COMPARE_AND_SWAP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_COMPARE_AND_SWAP ("<d>", "li");
-  else
-    loop = MIPS_COMPARE_AND_SWAP ("<d>", "move");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "32")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "li,move")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_required_oldval" "2")
+   (set_attr "sync_insn1_op2" "3")])
 
 (define_expand "sync_compare_and_swap<mode>"
   [(match_operand:SHORT 0 "register_operand")
@@ -85,15 +82,13 @@
 			     (match_operand:SI 5 "reg_or_0_operand" "d,J")]
 			    UNSPEC_COMPARE_AND_SWAP_12))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP);
-  else
-    loop = MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP);
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "40,36")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_inclusive_mask" "2")
+   (set_attr "sync_exclusive_mask" "3")
+   (set_attr "sync_required_oldval" "4")
+   (set_attr "sync_insn1_op2" "5")])
 
 (define_insn "sync_add<mode>"
   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
@@ -102,15 +97,10 @@
 		     (match_operand:GPR 1 "arith_operand" "I,d"))]
 	  UNSPEC_SYNC_OLD_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_OP ("<d>", "<d>addiu");
-  else
-    loop = MIPS_SYNC_OP ("<d>", "<d>addu");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "addiu,addu")
+   (set_attr "sync_mem" "0")
+   (set_attr "sync_insn1_op2" "1")])
 
 (define_expand "sync_<optab><mode>"
   [(set (match_operand:SHORT 0 "memory_operand")
@@ -138,11 +128,15 @@
 	  UNSPEC_SYNC_OLD_OP_12))
    (clobber (match_scratch:SI 4 "=&d"))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_AND);
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "40")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "<insn>")
+   (set_attr "sync_insn2" "and")
+   (set_attr "sync_mem" "0")
+   (set_attr "sync_inclusive_mask" "1")
+   (set_attr "sync_exclusive_mask" "2")
+   (set_attr "sync_insn1_op2" "3")
+   (set_attr "sync_oldval" "4")
+   (set_attr "sync_newval" "4")])
 
 (define_expand "sync_old_<optab><mode>"
   [(parallel [
@@ -175,11 +169,15 @@
 	  UNSPEC_SYNC_OLD_OP_12))
    (clobber (match_scratch:SI 5 "=&d"))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_AND);
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "40")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "<insn>")
+   (set_attr "sync_insn2" "and")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_inclusive_mask" "2")
+   (set_attr "sync_exclusive_mask" "3")
+   (set_attr "sync_insn1_op2" "4")
+   (set_attr "sync_newval" "5")])
 
 (define_expand "sync_new_<optab><mode>"
   [(parallel [
@@ -217,11 +215,15 @@
 	   (match_dup 3)
 	   (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_AND);
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "40")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "<insn>")
+   (set_attr "sync_insn2" "and")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_newval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_inclusive_mask" "2")
+   (set_attr "sync_exclusive_mask" "3")
+   (set_attr "sync_insn1_op2" "4")])
 
 (define_expand "sync_nand<mode>"
   [(set (match_operand:SHORT 0 "memory_operand")
@@ -249,11 +251,15 @@
 	  UNSPEC_SYNC_OLD_OP_12))
    (clobber (match_scratch:SI 4 "=&d"))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_XOR);
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "40")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "and")
+   (set_attr "sync_insn2" "xor")
+   (set_attr "sync_mem" "0")
+   (set_attr "sync_inclusive_mask" "1")
+   (set_attr "sync_exclusive_mask" "2")
+   (set_attr "sync_insn1_op2" "3")
+   (set_attr "sync_oldval" "4")
+   (set_attr "sync_newval" "4")])
 
 (define_expand "sync_old_nand<mode>"
   [(parallel [
@@ -284,11 +290,15 @@
 	  UNSPEC_SYNC_OLD_OP_12))
    (clobber (match_scratch:SI 5 "=&d"))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_XOR);
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "40")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "and")
+   (set_attr "sync_insn2" "xor")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_inclusive_mask" "2")
+   (set_attr "sync_exclusive_mask" "3")
+   (set_attr "sync_insn1_op2" "4")
+   (set_attr "sync_newval" "5")])
 
 (define_expand "sync_new_nand<mode>"
   [(parallel [
@@ -324,24 +334,27 @@
 	   (match_dup 3)
 	   (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_XOR);
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "40")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "and")
+   (set_attr "sync_insn2" "xor")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_newval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_inclusive_mask" "2")
+   (set_attr "sync_exclusive_mask" "3")
+   (set_attr "sync_insn1_op2" "4")])
 
 (define_insn "sync_sub<mode>"
   [(set (match_operand:GPR 0 "memory_operand" "+R")
 	(unspec_volatile:GPR
           [(minus:GPR (match_dup 0)
-			      (match_operand:GPR 1 "register_operand" "d"))]
+		      (match_operand:GPR 1 "register_operand" "d"))]
 	 UNSPEC_SYNC_OLD_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_OP ("<d>", "<d>subu");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "subu")
+   (set_attr "sync_mem" "0")
+   (set_attr "sync_insn1_op2" "1")])
 
 (define_insn "sync_old_add<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
@@ -352,15 +365,11 @@
 		     (match_operand:GPR 2 "arith_operand" "I,d"))]
 	 UNSPEC_SYNC_OLD_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
-  else
-    loop = MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "addiu,addu")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_insn "sync_old_sub<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d")
@@ -371,11 +380,11 @@
 		      (match_operand:GPR 2 "register_operand" "d"))]
 	 UNSPEC_SYNC_OLD_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "subu")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_insn "sync_new_add<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
@@ -386,15 +395,12 @@
 	  [(plus:GPR (match_dup 1) (match_dup 2))]
 	 UNSPEC_SYNC_NEW_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
-  else
-    loop = MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "addiu,addu")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_newval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_insn "sync_new_sub<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d")
@@ -405,11 +411,12 @@
 	  [(minus:GPR (match_dup 1) (match_dup 2))]
 	 UNSPEC_SYNC_NEW_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop = MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "subu")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_newval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_insn "sync_<optab><mode>"
   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
@@ -418,15 +425,10 @@
 			      (match_dup 0))]
 	 UNSPEC_SYNC_OLD_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_OP ("<d>", "<immediate_insn>");
-  else
-    loop = MIPS_SYNC_OP ("<d>", "<insn>");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
+   (set_attr "sync_mem" "0")
+   (set_attr "sync_insn1_op2" "1")])
 
 (define_insn "sync_old_<optab><mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
@@ -437,15 +439,11 @@
 			    (match_dup 1))]
 	 UNSPEC_SYNC_OLD_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
-  else
-    loop = MIPS_SYNC_OLD_OP ("<d>", "<insn>");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_insn "sync_new_<optab><mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
@@ -456,30 +454,23 @@
 			    (match_dup 1))]
 	 UNSPEC_SYNC_NEW_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
-  else
-    loop = MIPS_SYNC_NEW_OP ("<d>", "<insn>");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "28")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "<immediate_insn>,<insn>")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_newval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_insn "sync_nand<mode>"
   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
 	(unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
 	 UNSPEC_SYNC_OLD_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_NAND ("<d>", "andi");
-  else
-    loop = MIPS_SYNC_NAND ("<d>", "and");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "32")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "andi,and")
+   (set_attr "sync_insn2" "not")
+   (set_attr "sync_mem" "0")
+   (set_attr "sync_insn1_op2" "1")])
 
 (define_insn "sync_old_nand<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
@@ -488,15 +479,12 @@
         (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
 	 UNSPEC_SYNC_OLD_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_OLD_NAND ("<d>", "andi");
-  else
-    loop = MIPS_SYNC_OLD_NAND ("<d>", "and");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "32")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "andi,and")
+   (set_attr "sync_insn2" "not")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_insn "sync_new_nand<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
@@ -505,15 +493,13 @@
 	(unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
 	 UNSPEC_SYNC_NEW_OP))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_NEW_NAND ("<d>", "andi");
-  else
-    loop = MIPS_SYNC_NEW_NAND ("<d>", "and");
-  return mips_output_sync_loop (true, loop, operands);
-}
-  [(set_attr "length" "32")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_insn1" "andi,and")
+   (set_attr "sync_insn2" "not")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_newval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_insn "sync_lock_test_and_set<mode>"
   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
@@ -522,15 +508,12 @@
 	(unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
 	 UNSPEC_SYNC_EXCHANGE))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_EXCHANGE ("<d>", "li");
-  else
-    loop = MIPS_SYNC_EXCHANGE ("<d>", "move");
-  return mips_output_sync_loop (false, loop, operands);
-}
-  [(set_attr "length" "24")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_release_barrier" "no")
+   (set_attr "sync_insn1" "li,move")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   (set_attr "sync_insn1_op2" "2")])
 
 (define_expand "sync_lock_test_and_set<mode>"
   [(match_operand:SHORT 0 "register_operand")
@@ -546,20 +529,20 @@
 })
 
 (define_insn "test_and_set_12"
-  [(set (match_operand:SI 0 "register_operand" "=&d,&d")
-	(match_operand:SI 1 "memory_operand" "+R,R"))
+  [(set (match_operand:SI 0 "register_operand" "=&d")
+	(match_operand:SI 1 "memory_operand" "+R"))
    (set (match_dup 1)
-	(unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
-			     (match_operand:SI 3 "register_operand" "d,d")
-			     (match_operand:SI 4 "arith_operand" "d,J")]
+	(unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d")
+			     (match_operand:SI 3 "register_operand" "d")
+			     (match_operand:SI 4 "arith_operand" "dJ")]
 	  UNSPEC_SYNC_EXCHANGE_12))]
   "GENERATE_LL_SC"
-{
-  const char *loop;
-  if (which_alternative == 0)
-    loop = MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP);
-  else
-    loop = MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP);
-  return mips_output_sync_loop (false, loop, operands);
-}
-  [(set_attr "length" "28,24")])
+  { return mips_output_sync_loop (insn, operands); }
+  [(set_attr "sync_release_barrier" "no")
+   (set_attr "sync_oldval" "0")
+   (set_attr "sync_mem" "1")
+   ;; Unused, but needed to give the number of operands expected by
+   ;; the expander.
+   (set_attr "sync_inclusive_mask" "2")
+   (set_attr "sync_exclusive_mask" "3")
+   (set_attr "sync_insn1_op2" "4")])