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authorKazu Hirata <kazu@cs.umass.edu>2003-07-06 23:05:13 +0000
committerKazu Hirata <kazu@gcc.gnu.org>2003-07-06 23:05:13 +0000
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h8300.c: Fix comment typos.
* config/h8300/h8300.c: Fix comment typos. * config/h8300/h8300.md: Likewise. * config/i386/athlon.md: Likewise. * config/i386/i386.c: Likewise. * config/i386/pentium.md: Likewise. * config/ia64/ia64.c: Likewise. * config/ia64/itanium1.md: Likewise. * config/ia64/itanium2.md: Likewise. * config/m32r/m32r.md: Likewise. * config/m68hc11/m68hc11.c: Likewise. * config/mcore/mcore.c: Likewise. * config/mips/sr71k.md: Likewise. * config/mips/t-iris5-as: Likewise. * config/mmix/mmix.h: Likewise. * config/ns32k/ns32k.h: Likewise. * config/ns32k/NOTES: Fix a typo. From-SVN: r69021
Diffstat (limited to 'gcc/config/mips/sr71k.md')
-rw-r--r--gcc/config/mips/sr71k.md6
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/mips/sr71k.md b/gcc/config/mips/sr71k.md
index 76417b6..d6c7caf 100644
--- a/gcc/config/mips/sr71k.md
+++ b/gcc/config/mips/sr71k.md
@@ -2,7 +2,7 @@
;;
;; DFA-based pipeline description for Sandcraft SR3 (MIPS64 based)
;;
-;; The SR3 is describeds as:
+;; The SR3 is described as:
;; - nine-stage pipeline, insn buffering with out-of-order issue to
;; multiple function units, with an average dispatch rate of 2
;; insn.s per cycle (max 6 insns: 2 fpu, 4 cpu).
@@ -22,8 +22,8 @@
;;
;;
;; Reservation model is based on:
-;; 1) Figure 6-1, from the 1.0 specicification.
-;; 2) Chapter 19, from the 1.0 specificication.
+;; 1) Figure 6-1, from the 1.0 specification.
+;; 2) Chapter 19, from the 1.0 specification.
;; 3) following questions(Red Hat)/answers(Sandcraft):
;; RH> From Section 19.1
;; RH> 1) In terms of figure 6-1, are all the instructions in