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| author | Richard Sandiford <rsandifo@redhat.com> | 2005-03-11 16:38:27 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2005-03-11 16:38:27 +0000 |
| commit | 0ac40e7a866e3b149bdeacbf5cc36d1fe364a952 (patch) | |
| tree | 6d67d7deaee3c8d2c5daab6e5ceec21a45c98736 /gcc/config/mips/mips.md | |
| parent | 266c6b40edea65bc1159fa60a229b7d8182412ff (diff) | |
| download | gcc-0ac40e7a866e3b149bdeacbf5cc36d1fe364a952.zip gcc-0ac40e7a866e3b149bdeacbf5cc36d1fe364a952.tar.gz gcc-0ac40e7a866e3b149bdeacbf5cc36d1fe364a952.tar.bz2 | |
mips.h (mips_fix_vr4130_string): Declare.
* config/mips/mips.h (mips_fix_vr4130_string): Declare.
(TARGET_FIX_VR4130): New macro.
(TARGET_OPTIONS): Add -mfix-vr4130.
(ISA_HAS_MACCHI): New macro.
(ASM_SPEC): Add -mfix-vr4130.
* config/mips/mips.c (mips_fix_vr4130_string): New variable.
(override_options): Handle mips_fix_vr4130_string.
(mips_avoid_hazards): Clear all_noreorder_p
if we're working around VR4130 errata and the macc alternatives
are not available.
* config/mips/mips.md (mfhilo_<mode>): Turn into a define_expand.
(*mfhilo_<mode>, *mfhilo_<mode>_macc): New insns.
* config/mips/vr.h (DEFAULT_VR_ARCH): Set to mfix-vr4130.
(MULTILIB_DEFAULTS): Remove leading "march=".
(DRIVER_SELF_SPECS): Likewise. Make -mfix-vr4130 imply -march=vr4130
if no architecture option is given.
* config/mips/t-vr (MULTILIB_OPTIONS): Use -mfix-vr4130 for the
VR4130 multilibs.
(MULTILIB_MATCHES): Map -march=vr4130 to the -mfix-vr4130 multilibs.
* doc/invoke.texi: Document -mfix-vr4130.
From-SVN: r96301
Diffstat (limited to 'gcc/config/mips/mips.md')
| -rw-r--r-- | gcc/config/mips/mips.md | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 8c3a80a..0a63df0 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3729,17 +3729,42 @@ beq\t%2,%.,1b\;\ ;; ;; We cope with this by making the mflo and mfhi patterns use both HI and LO. ;; Operand 1 is the register we want, operand 2 is the other one. +;; +;; When generating VR4120 or VR4130 code, we use macc{,hi} and +;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal +;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130. + +(define_expand "mfhilo_<mode>" + [(set (match_operand:GPR 0 "register_operand") + (unspec:GPR [(match_operand:GPR 1 "register_operand") + (match_operand:GPR 2 "register_operand")] + UNSPEC_MFHILO))]) -(define_insn "mfhilo_<mode>" +(define_insn "*mfhilo_<mode>" [(set (match_operand:GPR 0 "register_operand" "=d,d") (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") (match_operand:GPR 2 "register_operand" "l,h")] UNSPEC_MFHILO))] - "" + "!ISA_HAS_MACCHI" "mf%1\t%0" [(set_attr "type" "mfhilo") (set_attr "mode" "<MODE>")]) +(define_insn "*mfhilo_<mode>_macc" + [(set (match_operand:GPR 0 "register_operand" "=d,d") + (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l") + (match_operand:GPR 2 "register_operand" "l,h")] + UNSPEC_MFHILO))] + "ISA_HAS_MACCHI" +{ + if (REGNO (operands[1]) == HI_REGNUM) + return "<d>macchi\t%0,%.,%."; + else + return "<d>macc\t%0,%.,%."; +} + [(set_attr "type" "mfhilo") + (set_attr "mode" "<MODE>")]) + ;; Patterns for loading or storing part of a paired floating point ;; register. We need them because odd-numbered floating-point registers ;; are not fully independent: see mips_split_64bit_move. |