diff options
| author | Mingming Sun <mingm.sun@gmail.com> | 2010-11-13 17:30:52 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2010-11-13 17:30:52 +0000 |
| commit | 98824c6fc45b6262b807091ec68193decef6ba0c (patch) | |
| tree | 53f9a44051921b255a54a1aa8a6d35a6648ac8e1 /gcc/config/mips/mips.h | |
| parent | 989b59db15278ce97f73b7c1fdb56959241cca01 (diff) | |
| download | gcc-98824c6fc45b6262b807091ec68193decef6ba0c.zip gcc-98824c6fc45b6262b807091ec68193decef6ba0c.tar.gz gcc-98824c6fc45b6262b807091ec68193decef6ba0c.tar.bz2 | |
invoke.texi (MIPS Options): Add loongson3a processor.
gcc/
2010-09-21 Mingming Sun <mingm.sun@gmail.com>
* doc/invoke.texi (MIPS Options): Add loongson3a processor.
* config/mips/mips.md (define_attr "cpu"): Add loongson_3a.
(define_insn "prefetch"): Add TARGET_LOONGSON_3A.
* config/mips/mips.h (TARGET_LOONGSON_3A): Define.
(TUNE_LOONGSON_3A): Define.
(TARGET_LOONGSON_VECTORS): Add TARGET_LOONGSON_3A.
(MIPS_ISA_LEVEL_SPEC): Add loongson3a.
* config/mips/mips.c (mips_cpu_info_table): Add loongson3a.
(mips_issue_rate): Add PROCESSOR_LOONGSON_3A.
(mips_rtx_cost_data): Add Loongson-3A.
From-SVN: r166716
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 7b5e140..392e457 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -218,6 +218,7 @@ enum mips_code_readable_setting { #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) +#define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A) #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) @@ -242,6 +243,7 @@ enum mips_code_readable_setting { || mips_tune == PROCESSOR_74KF3_2) #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ || mips_tune == PROCESSOR_LOONGSON_2F) +#define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A) #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) @@ -261,7 +263,8 @@ enum mips_code_readable_setting { Loongson-2E/2F processors should be enabled. In o32 pairs of floating-point registers provide 64-bit values. */ #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \ - && TARGET_LOONGSON_2EF) + && (TARGET_LOONGSON_2EF \ + || TARGET_LOONGSON_3A)) /* True if the pre-reload scheduler should try to create chains of multiply-add or multiply-subtract instructions. For example, @@ -716,7 +719,7 @@ enum mips_code_readable_setting { %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ |march=34k*|march=74k*|march=1004k*: -mips32r2} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ - |march=xlr: -mips64} \ + |march=xlr|march=loongson3a: -mips64} \ %{march=mips64r2|march=octeon: -mips64r2} \ %{!march=*: -" MULTILIB_ISA_DEFAULT "}}" |