mips-protos.h (mips_cfun_has_cprestore_slot_p): Declare.

gcc/
	* config/mips/mips-protos.h (mips_cfun_has_cprestore_slot_p): Declare.
	(mips_cprestore_address_p): Likewise.
	(mips_save_gp_to_cprestore_slot): Likewise.
	(mips_restore_gp): Rename to...
	(mips_restore_gp_from_cprestore_slot): ...this.
	(mips_must_initialize_gp_p): Declare.
	(mips_emit_save_slot_move): Likewise.
	(mips_output_load_label): Return nothing.
	(mips_eh_uses): Declare.
	* config/mips/mips.h (TARGET_SPLIT_CALLS): Require epilogue_completed.
	(TARGET_CPRESTORE_DIRECTIVE): New macro.
	(TARGET_ABSOLUTE_JUMPS): Likewise.
	(EH_USES): Likewise.
	(FIRST_PSEUDO_REGISTER): Update comment.
	(MIPS_ABSOLUTE_JUMP): New macro, extracted from...
	(MIPS_CALL): ...here.
	(REGISTER_NAMES): Add $cprestore.
	* config/mips/mips.c (machine_function): Remove has_gp_insn_p.
	Add load_label_length, has_inflexible_gp_insn_p,
	has_flexible_gp_insn_p, must_initialize_gp_p and
	must_restore_gp_when_clobbered_p.
	(mips_expand_call): Don't generate split instructions here.
	(mips_split_call): Update the call to mips_restore_gp after
	the above name change.
	(mips16_cfun_returns_in_fpr_p): Move earlier in file.
	(mips_find_gp_ref): New function.
	(mips_insn_has_inflexible_gp_ref_p): Likewise.
	(mips_cfun_has_inflexible_gp_ref_p): Likewise.
	(mips_insn_has_flexible_gp_ref_p): Likewise.
	(mips_cfun_has_flexible_gp_ref_p): Likewise.
	(mips_function_has_gp_insn): Delete.
	(mips_global_pointer): Drop the df_regs_ever_live_p check.
	Use the new functions above.  Only return INVALID_REGNUM
	for TARGET_ABSOLUTE_JUMPS.
	(mips_must_initialize_gp_p): New function.
	(mips_get_cprestore_base_and_offset): New function, extracted from...
	(mips_cprestore_slot): ...here.  Take a bool parameter.
	(mips_cfun_has_cprestore_slot_p): New function.
	(mips_cprestore_address_p): Likewise.
	(mips_save_gp_to_cprestore_slot): Likewise.
	(mips_restore_gp): Rename to...
	(mips_restore_gp_from_cprestore_slot): ...this.  Assert
	epilogue_completed.  Update the call to mips_cprestore_slot.
	Test cfun->machine->must_restore_gp_when_clobbered_p.
	(mips_direct_save_slot_move_p): New function.
	(mips_emit_save_slot_move): Likewise.
	(mips_output_cplocal): Test mips_must_initialize_gp_p () instead
	of cfun->machine->global_pointer.
	(mips_output_function_prologue): Check mips_must_initialize_gp_p ().
	(mips_save_reg): Use mips_emit_save_slot_move.
	(mips_expand_prologue): Set must_initialize_gp_p.
	Use mips_cfun_has_cprestore_slot_p.  Use gen_potential_cprestore
	for all cprestore saves.  Emit a use_cprestore instruction after
	setting up the cprestore slot.
	(mips_restore_reg): Use mips_emit_save_slot_move.
	(mips_process_load_label): New function.
	(mips_load_label_length): Likewise.
	(mips_output_load_label): Don't return asm: output it here instead.
	Use mips_process_load_label.
	(mips_adjust_insn_length): Adjust the length of branch instructions
	that have length MAX_PIC_BRANCH_LENGTH.
	(mips_output_conditional_branch): Update the call to
	mips_output_load_label.  Assume the branch target is OPERANDS[0]
	rather than OPERANDS[1].  Use MIPS_ABSOLUTE_JUMP for absolute jumps.
	(mips_output_order_conditional_branch): Swap the meaning of
	OPERANDS[0] and OPERANDS[1].
	(mips_variable_issue): Don't count ghost instructions.
	(mips_expand_ghost_gp_insns): New function.
	(mips_reorg): Rerun mips_reorg_process_insns if it returns true.
	(mips_output_mi_thunk): Set must_initialize_gp_p.
	(mips_eh_uses): New function.
	* config/mips/predicates.md (cprestore_save_slot_operand)
	(cprestore_load_slot_operand): New predicates.
	* config/mips/mips.md (UNSPEC_POTENTIAL_CPRESTORE): New unspec.
	(UNSPEC_MOVE_GP): Likewise.
	(UNSPEC_CPRESTORE, UNSPEC_RESTORE_GP, UNSPEC_EH_RETURN)
	(UNSPEC_CONSTTABLE_INT, UNSPEC_CONSTTABLE_FLOAT): Bump to make room.
	(CPRESTORE_SLOT_REGNUM): New register.
	(MAX_PIC_BRANCH_LENGTH): New constant.
	(jal_macro): Use MIPS_ABSOLUTE_JUMPS.
	(length): Use MAX_PIC_BRANCH_LENGTH as a placeholder for PIC long
	branches.  Fix commentary.
	(loadgp_newabi_<mode>): Change from unspec_volatile to unspec.
	Only split if mips_must_initialize_gp_p; expand to nothing otherwise.
	Change type to "ghost".
	(loadgp_absolute_<mode>): Likewise.
	(loadgp_rtp_<mode>): Likewise.
	(copygp_mips16): Likewise.
	(loadgp_blockage): Remove redundant mode attribute.
	(potential_cprestore): New instruction.
	(cprestore): Turn into an unspec set.
	(use_cprestore): New instruction.
	(*branch_fp): Swap operands 0 and 1.  Remove redundant mode attribute.
	(*branch_fp_inverted): Likewise.
	(*branch_order<mode>): Likewise.
	(*branch_order<mode>_inverted): Likewise.
	(*branch_equality<mode>): Likewise.
	(*branch_equality<mode>_inverted): Likewise.
	(*branch_bit<bbv><mode>): Likewise.
	(*branch_bit<bbv><mode>_inverted): Likewise.
	(*branch_equality<mode>_mips16): Remove redundant mode.
	(jump): Turn into a define_expand.
	(*jump_absolute): New instruction.
	(*jump_pic): Likewise.
	(*jump_mips16): Rename previously-unnamed pattern.  Remove
	redundant mode attribute.
	(restore_gp): Split on epilogue_completed rather than
	reload_completed.  Change type to "ghost".
	(move_gp<mode>): New instruction.
	* config/mips/mips-dsp.md (mips_bposge): Swap operands 0 and 1.
	Remove redundant mode attribute.
	* config/mips/mips-ps-3d.md (bc1any4t): Likewise.
	(bc1any4f, bc1any2t, bc1any2f): Likewise.
	(*branch_upper_lower, *branch_upper_lower_inverted): Likewise.

gcc/testsuite/
	* gcc.target/mips/branch-helper.h: New file.
	* gcc.target/mips/branch-2.c,
	* gcc.target/mips/branch-3.c,
	* gcc.target/mips/branch-4.c,
	* gcc.target/mips/branch-5.c,
	* gcc.target/mips/branch-6.c,
	* gcc.target/mips/branch-7.c,
	* gcc.target/mips/branch-8.c,
	* gcc.target/mips/branch-9.c,
	* gcc.target/mips/branch-10.c,
	* gcc.target/mips/branch-11.c,
	* gcc.target/mips/branch-12.c,
	* gcc.target/mips/branch-13.c,
	* gcc.target/mips/branch-14.c,
	* gcc.target/mips/branch-15.c: New tests.

From-SVN: r151695

1 files changed, 30 insertions, 10 deletions

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 352dbd2..eda7447 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -161,10 +161,13 @@ enum mips_code_readable_setting {
 
 /* True if the call patterns should be split into a jalr followed by
    an instruction to restore $gp.  It is only safe to split the load
-   from the call when every use of $gp is explicit.  */
+   from the call when every use of $gp is explicit.
+
+   See mips_must_initialize_gp_p for details about how we manage the
+   global pointer.  */
 
 #define TARGET_SPLIT_CALLS \
-  (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
+  (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
 
 /* True if we're generating a form of -mabicalls in which we can use
    operators like %hi and %lo to refer to locally-binding symbols.
@@ -202,6 +205,17 @@ enum mips_code_readable_setting {
 /* True if TARGET_USE_GOT and if $gp is a call-saved register.  */
 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
 
+/* True if we should use .cprestore to store to the cprestore slot.
+
+   We continue to use .cprestore for explicit-reloc code so that JALs
+   inside inline asms will work correctly.  */
+#define TARGET_CPRESTORE_DIRECTIVE \
+  (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
+
+/* True if we can use the J and JAL instructions.  */
+#define TARGET_ABSOLUTE_JUMPS \
+  (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
+
 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
    This is true for both the PIC and non-PIC VxWorks RTP modes.  */
 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
@@ -1300,6 +1314,8 @@ enum mips_code_readable_setting {
 
 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
 
+#define EH_USES(N) mips_eh_uses (N)
+
 /* Offsets recorded in opcodes are a multiple of this alignment factor.
    The default for this in 64-bit mode is 8, which causes problems with
    SFmode register saves.  */
@@ -1543,11 +1559,12 @@ enum mips_code_readable_setting {
    - 8 condition code registers
    - 2 accumulator registers (hi and lo)
    - 32 registers each for coprocessors 0, 2 and 3
-   - 3 fake registers:
+   - 4 fake registers:
 	- ARG_POINTER_REGNUM
 	- FRAME_POINTER_REGNUM
 	- GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
-   - 3 dummy entries that were used at various times in the past.
+	- CPRESTORE_SLOT_REGNUM
+   - 2 dummy entries that were used at various times in the past.
    - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
    - 6 DSP control registers  */
 
@@ -2661,6 +2678,13 @@ typedef struct mips_args {
 #define MIPS_BRANCH(OPCODE, OPERANDS) \
   "%*" OPCODE "%?\t" OPERANDS "%/"
 
+/* Return an asm string that forces INSN to be treated as an absolute
+   J or JAL instruction instead of an assembler macro.  */
+#define MIPS_ABSOLUTE_JUMP(INSN) \
+  (TARGET_ABICALLS_PIC2						\
+   ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2"		\
+   : INSN)
+
 /* Return the asm template for a call.  INSN is the instruction's mnemonic
    ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
    of the target.
@@ -2675,11 +2699,7 @@ typedef struct mips_args {
    ? "%*" INSN "\t%" #OPNO "%/"					\
    : REG_P (OPERANDS[OPNO])					\
    ? "%*" INSN "r\t%" #OPNO "%/"				\
-   : TARGET_ABICALLS_PIC2					\
-   ? (".option\tpic0\n\t"					\
-      "%*" INSN "\t%" #OPNO "%/\n\t"				\
-      ".option\tpic2")						\
-   : "%*" INSN "\t%" #OPNO "%/")
+   : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #OPNO "%/"))
 
 /* Control the assembler format that we output.  */
 
@@ -2707,7 +2727,7 @@ typedef struct mips_args {
   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",	   \
   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",	   \
   "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",	   \
-  "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec",		   \
+  "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec",	   \
   "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",  \
   "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
   "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \