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| author | Vladimir Makarov <vmakarov@redhat.com> | 2011-03-28 01:53:24 +0000 |
|---|---|---|
| committer | Vladimir Makarov <vmakarov@gcc.gnu.org> | 2011-03-28 01:53:24 +0000 |
| commit | 99710245becabdfa97984d1f68a01f9876124417 (patch) | |
| tree | 761665b37aeeeb5eb4e3f9b4770772ea49679cc0 /gcc/config/mips/mips.c | |
| parent | 0854e22029b6d45bc67140bf5d5493ee5c9294ef (diff) | |
| download | gcc-99710245becabdfa97984d1f68a01f9876124417.zip gcc-99710245becabdfa97984d1f68a01f9876124417.tar.gz gcc-99710245becabdfa97984d1f68a01f9876124417.tar.bz2 | |
re PR bootstrap/48307 (Bootstrap failure)
2011-03-27 Vladimir Makarov <vmakarov@redhat.com>
PR bootstrap/48307
Revert the previous patch.
From-SVN: r171589
Diffstat (limited to 'gcc/config/mips/mips.c')
| -rw-r--r-- | gcc/config/mips/mips.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 643e507..0692902 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -11017,6 +11017,29 @@ mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in) + memory_move_secondary_cost (mode, rclass, in)); } +/* Implement TARGET_IRA_COVER_CLASSES. */ + +static const reg_class_t * +mips_ira_cover_classes (void) +{ + static const reg_class_t acc_classes[] = { + GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS, + ST_REGS, LIM_REG_CLASSES + }; + static const reg_class_t no_acc_classes[] = { + GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS, + ST_REGS, LIM_REG_CLASSES + }; + + /* Don't allow the register allocators to use LO and HI in MIPS16 mode, + which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS + as a cover class only works well when we keep per-register costs. + Using it when not optimizing can cause us to think accumulators + have the same cost as GPRs in cases where GPRs are actually much + cheaper. */ + return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes; +} + /* Return the register class required for a secondary register when copying between one of the registers in RCLASS and value X, which has mode MODE. X is the source of the move if IN_P, otherwise it @@ -16595,6 +16618,9 @@ mips_shift_truncation_mask (enum machine_mode mode) #undef TARGET_DWARF_REGISTER_SPAN #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span +#undef TARGET_IRA_COVER_CLASSES +#define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes + #undef TARGET_ASM_FINAL_POSTSCAN_INSN #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn |