mips.c (mips_use_dfa_pipeline_interface): Add R3000.

2004-06-23  Eric Christopher  <echristo@redhat.com>

	* config/mips/mips.c (mips_use_dfa_pipeline_interface): Add R3000.
	* config/mips/mips.md: Remove R3000 scheduling description.
	* config/mips/3000.md: New file.

From-SVN: r83575

1 files changed, 69 insertions, 0 deletions

diff --git a/gcc/config/mips/3000.md b/gcc/config/mips/3000.md
new file mode 100644
index 0000000..9282597
--- /dev/null
+++ b/gcc/config/mips/3000.md
@@ -0,0 +1,69 @@
+;; DFA based pipeline description for the r3000
+;; This is a special pipeline - this is also the default schedule and
+;; so we need to schedule instructions that may not exist on the r2k/r3k.
+
+;; Generic processor description that assumes that the only latencies are for
+;; hazards or delay slots, otherwise everything is assumed to issue and execute
+;; in one cycle.
+(define_automaton "r3k")
+
+(define_cpu_unit "r3k_alu" "r3k")
+
+(define_insn_reservation "r3k_generic_alu" 1
+  (and (eq_attr "cpu" "r3000")
+       (eq_attr "type" "unknown,prefetch,prefetchx,condmove,mthilo,const,arith,shift,slt,clz,trap,fmove,fadd,fmadd,fabs,fneg,fcvt,fsqrt,frsqrt,multi,nop"))
+  "r3k_alu")
+
+(define_insn_reservation "r3k_load_alu" 2
+  (and (eq_attr "cpu" "r3000")
+       (eq_attr "type" "load, fpload, fpidxload, xfer"))
+  "r3k_alu*2")
+
+(define_insn_reservation "r3k_call_alu" 2
+  (and (eq_attr "cpu" "r3000")
+       (eq_attr "type" "branch,jump,call"))
+  "r3k_alu*2")
+
+(define_insn_reservation "r3k_hilo_alu" 3
+  (and (eq_attr "cpu" "r3000")
+       (eq_attr "type" "mfhilo"))
+  "r3k_alu*3")
+
+(define_insn_reservation "r3k_fcmp_alu" 2
+  (and (eq_attr "cpu" "r3000")
+       (eq_attr "type" "fcmp, fadd"))
+  "r3k_alu*2")
+
+(define_insn_reservation "r3k_imul_alu" 12
+  (and (eq_attr "cpu" "r3000")
+       (eq_attr "type" "imul, imadd"))
+  "r3k_alu*12")
+
+(define_insn_reservation "r3k_idiv_alu" 35
+  (and (eq_attr "cpu" "r3000")
+       (eq_attr "type" "idiv"))
+  "r3k_alu*35")
+
+(define_insn_reservation "r3k_fmul_single_alu" 4
+  (and (eq_attr "cpu" "r3000")
+       (and (eq_attr "type" "fmul")
+	    (eq_attr "mode" "SF")))
+  "r3k_alu*4")
+
+(define_insn_reservation "r3k_fmul_double_alu" 5
+  (and (eq_attr "cpu" "r3000")
+       (and (eq_attr "type" "fmul")
+	    (eq_attr "mode" "DF")))
+  "r3k_alu*5")
+
+(define_insn_reservation "r3k_fdiv_single_alu" 12
+  (and (eq_attr "cpu" "r3000")
+       (and (eq_attr "type" "fdiv")
+	    (eq_attr "mode" "SF")))
+  "r3k_alu*12")
+
+(define_insn_reservation "r3k_fdiv_double_alu" 19
+  (and (eq_attr "cpu" "r3000")
+       (and (eq_attr "type" "fdiv")
+	    (eq_attr "mode" "DF")))
+  "r3k_alu*19")