Cleanup ColdFire scheduling support and add V4 pipeline model.

	* config/m68k/m68k.md (UNSPEC_TIE): New constant.
	(define_attr cpu): Add cfv4 value.
	(define_attr type, define_attr type1): Merge into a single 'type'
	attribute.  Update all uses.
	(define_attr opx_type, define_attr opy_type, define_attr opx_access):
	Rearrange and update.  Rename value 'reg' to 'Rn', add value 'FPn'.
	Update all uses.
	(define_attr opx_mem, define_attr opy_mem): Remove.
	(define_attr op_mem): Clean up, update comment.
	(define_attr size): Use specific values instead of general int.
	(define_attr guess, define_attr split): Remove.  Update all uses.
	(movdf_internal, tstsi_internal, tsthi_internal, tstqi_internal,
	tst<mode>_68881, pushexthisi_const, movsi_const0_68000_10,
	movsi_const0_68040_60, movsi_const0, movsi_cf, movstrictqi_cf,
	zero_extendhisi2_cf, zero_extendqisi2_cfv4, cfv4_extendhisi2,
	68k_extendhisi2, extendqihi2, cfv4_extendqisi2, 68k_extendqisi2,
	floatsi<mode>2_68881, ftrunc<mode>2_68881, ftrunc<mode>2_cf,
	fix<mode>qi2_68881, fix<mode>hi2_68881, fix<mode>si2_68881,
	adddi_dishl32, addsi3_5200, add<mode>3_floatsi_68881,
	add<mode>3_floathi_68881, add<mode>3_floatqi_68881,
	add<mode>3_68881, add<mode>3_cf, subdi_dishl32, subsi3,
	sub<mode>3_floatsi_68881, sub<mode>3_floathi_68881,
	sub<mode>3_floatqi_68881, sub<mode>3_68881, sub<mode>3_cf,
	mulhi3, mulhisi3, mulhisisi3_s, mulsi3_68020, mulsi3_cf,
	umulhisi3, mulhisisi3_z, mul<mode>3_floatsi_68881,
	mul<mode>3_floathi_68881, mul<mode>3_floatqi_68881, fmul<mode>3_cf,
	div<mode>3_cf, sqrt<mode>2_cf, abs<mode>2_cf, clzsi2,
	one_cmplsi2_5200, subreghi1ashrdi_const32, ashrsi3, lshrsi3,
	bsetmemqi, bsetmemqi_ext, bclrmemqi, bclrmemqi_ext,
	beq, bne, bgt, blt, bordered, bunordered, buneq, bunge, bungt, bunle,
	bunlt, bltgt, tablejump_internal, call, non_symbolic_call_value,
	symbolic_call_value_jsr, symbolic_call_value_bsr, link):
	Update or set attributes.
	(stack_tie): New fake instruction.

	* config/m68k/m68k.h (TUNE_CFV4): New macro.
	(m68k_sched_attr_size): Update declaration.
	(m68k_sched_attr_type2): Remove.
	(m68k_sched_address_bypass_p, m68k_sched_indexed_address_bypass_p):
	Declare new bypass predicates.

	* config/m68k/m68k.c (m68k_sched_issue_rate,
	m68k_sched_first_cycle_multipass_dfa_lookahead): Declare hook
	implementations.
	(TARGET_SCHED_ISSUE_RATE,
	TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): Override hooks.
	(override_options): Handle scheduling for ColdFire V4 core.
	(m68k_expand_prologue): Emit stack_tie.
	(enum attr_op_type): Split value 'OP_TYPE_REG' to 'OP_TYPE_RN' and
	'OP_TYPE_FPN'.  Update all uses.
	(sched_guess_p): Remove.
	(sched_address_type): Handle symbolic addresses.
	(sched_get_operand): New static function.
	(sched_operand_type): Merge into sched_attr_op_type.
	(sched_attr_op_type): Handle FP registers, handle quick constants,
	update.
	(m68k_sched_attr_opx_type, m68k_sched_attr_opy_type): Update.
	(m68k_sched_attr_size): Update.  Move logic to ...
	(sched_get_attr_size_int): New static function.
	(sched_get_opxy_mem_type): New static function.
	(m68k_sched_attr_op_mem): Update.
	(m68k_sched_attr_type2): Remove.
	(sched_cfv4_bypass_data): New static variable.
	(m68k_sched_adjust_cost): Handle ColdFire V4 bypass.
	(m68k_sched_issue_rate): Implement scheduler hook.
	(struct _sched_ib: enabled_p): New field.
	(m68k_sched_variable_issue): Update.  Handle V4.
	(SCHED_DUMP_TODO, SCHED_DUMP_DONE, SCHED_DUMP_NOTHING,
	sched_dump_class_func_t, sched_dump_split_class,
	sched_dump_dfa_guess_unit_code, sched_dump_dfa_state,
	sched_dump_dfa_class, m68k_sched_dump): Remove.
	(m68k_sched_first_cycle_multipass_dfa_lookahead): Implement scheduler
	hook.
	(m68k_sched_init_global): Remove statisctics dumping, introduce
	sanity check that all instructions have pipeline reservations.  Handle
	ColdFire V4 core.
	(m68k_sched_dfa_pre_advance_cycle, m68k_sched_dfa_post_advance_cycle):
	Handle ColdFire V4 core.
	(sched_mem_operand_p, sched_get_reg_operand, sched_get_mem_operand):
	New static functions.
	(m68k_sched_address_bypass_p): New bypass predicate.
	(sched_get_indexed_address_scale): New static function.
	(m68k_sched_indexed_address_bypass_p): New bypass predicate.

	* cf.md: Update comments.
	(define_attr type2): Remove.  Use 'type' attribute instead.
	Update all uses.
	(cf_ib): Rename to cfv123_ib.  Update all uses.
	(cf_oep): Rename to cfv123_oep.  Update all uses.
	(cf_chr): Rename to cfv123_chr.  Update all uses.
	(cf_mem): Rename to cfv123_mem.  Update all uses.
	(cf_mac): Move to more appropriate place.
	(cfv123_guess): New automaton and cpu_unit.
	(cfv123_*, cfv12_*, cfv1_*, cfv2_*, cfv3_*): Use type attribute.
	Update uses of 'size' attribute.  Handle before reload scheduling.
	(cfv123_guess): New dummy reservation for unhandled instructions.
	(cfv4_*): Pipeline description of ColdFire V4 core.
	(ignore): New reservation to handle 'ignore' type.

From-SVN: r135033

1 files changed, 220 insertions, 269 deletions

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index abe363e..d142861 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -115,6 +115,7 @@
    (UNSPEC_COS 2)
    (UNSPEC_GOT 3)
    (UNSPEC_IB 4)
+   (UNSPEC_TIE 5)
   ])
 
 ;; UNSPEC_VOLATILE usage:
@@ -144,202 +145,104 @@
 ;; ::::::::::::::::::::
 
 ;; Processor type.
-(define_attr "cpu" "cfv1, cfv2, cfv3, unknown"
+(define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown"
   (const (symbol_ref "m68k_sched_cpu")))
 
 ;; MAC type.
 (define_attr "mac" "no, cf_mac, cf_emac"
   (const (symbol_ref "m68k_sched_mac")))
 
-;; Instruction type.
-;; Basically, an asm pattern.
-(define_attr "type"
-  "add_l, addq_l, asr_l, bcc, bclr, bra, bset, bsr,
-   clr_b, clr_w, clr_l, cmp_l,
-   ext_w, extb_l, ext_l,
-   fadd, fcmp, fdiv, ff1, fintrz, fmove, fmul, fsqrt, fsub, ftst, jmp, jsr,
-   ib,
-   lea, lsr_l,
-   move_b, move_w, move_l, moveq_l, mov3q_l, mvs_b, mvs_w, mvz_b, mvz_w,
-   muls_w, muls_l, mulu_w, mulu_l,
-   neg_l, nop, not_l,
-   pea, rts,
-   scc, sub_l, subq_l,
-   trap, tst_b, tst_l, tst_w,
-   unlk, unknown"
-  (const_string "unknown"))
-
 ;; Instruction type for use in scheduling description.
 ;; _l and _w suffixes indicate size of the operands of instruction.
 ;; alu - usual arithmetic or logic instruction.
-;; alu_reg1 - arithmetic or logic instruction with one operand that is
-;;            a register.
-;; alu_regx - arithmetic or logic instruction which has a register for its
-;;            X operand.
 ;; aluq - arithmetic or logic instruction which has a quick immediate (the one
 ;;        that is encoded in the instruction word) for its Y operand.
-;; <all other values> - corresponding asm instructions.
-(define_attr "type1"
-  "alu_l, alu_reg1, alu_regx, aluq_l, bcc, bra, bsr, clr, cmp_l, jmp, jsr, lea,
-   mov3q_l, move, move_l, moveq_l, mul_l, mul_w, pea, rts, tst, tst_l, unlk,
+;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx).
+;; bcc - conditional branch.
+;; bitr - bit operation that only updates flags.
+;; bitrw - bit operation that updates flags and output operand.
+;; bra, bsr, clr, cmp, div, ext - corresponding instruction.
+;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding
+;;                                                          instruction.
+;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction
+;;      buffer.
+;; ignore - fake instruction.
+;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction.
+;; mvsz - mvs or mvz instruction.
+;; neg, nop, pea, rts, scc - corresponding instruction.
+;; shift - arithmetic or logical shift instruction.
+;; trap, tst, unlk - corresponding instruction.
+(define_attr "type"
+  "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l,
+   div_w,div_l,ext,
+   falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst,
+   ib,ignore,
+   jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop,
+   pea,rts,scc,shift,
+   trap,tst,tst_l,unlk,
    unknown"
-  (cond [(eq_attr "type" "add_l,sub_l") (const_string "alu_l")
-	 (eq_attr "type" "ext_w,extb_l,ext_l,neg_l,not_l")
-	 (const_string "alu_reg1")
-	 (eq_attr "type" "asr_l,lsr_l") (const_string "alu_regx")
-	 (eq_attr "type" "addq_l,subq_l") (const_string "aluq_l")
-	 (eq_attr "type" "bcc") (const_string "bcc")
-	 (eq_attr "type" "bra") (const_string "bra")
-	 (eq_attr "type" "bsr") (const_string "bsr")
-	 (eq_attr "type" "clr_b,clr_l,clr_w") (const_string "clr")
-	 (eq_attr "type" "cmp_l") (const_string "cmp_l")
-	 (eq_attr "type" "jmp") (const_string "jmp")
-	 (eq_attr "type" "jsr") (const_string "jsr")
-	 (eq_attr "type" "lea") (const_string "lea")
-	 (eq_attr "type" "mov3q_l") (const_string "mov3q_l")
-	 (eq_attr "type" "move_b,move_w") (const_string "move")
-	 (eq_attr "type" "move_l") (const_string "move_l")
-	 (eq_attr "type" "moveq_l") (const_string "moveq_l")
-	 (eq_attr "type" "muls_l,mulu_l") (const_string "mul_l")
-	 (eq_attr "type" "muls_w,mulu_w") (const_string "mul_w")
-	 (eq_attr "type" "pea") (const_string "pea")
-	 (eq_attr "type" "rts") (const_string "rts")
-	 (eq_attr "type" "tst_b,tst_w") (const_string "tst")
-	 (eq_attr "type" "tst_l") (const_string "tst_l")
-	 (eq_attr "type" "unlk") (const_string "unlk")]
-	(const_string "unknown")))
+  (const_string "unknown"))
 
 ;; Index of the X or Y operand in recog_data.operand[].
 ;; Should be used only within opx_type and opy_type.
 (define_attr "opx" "" (const_int 0))
 (define_attr "opy" "" (const_int 1))
 
-;; Type of the X operand.
-;; See m68k.c: enum attr_op_type.
-(define_attr "opx_type"
-  "none, reg, mem1, mem234, mem5, mem6, mem7, imm_q, imm_w, imm_l"
-  (cond [(eq_attr "type1" "rts,unlk") (const_string "none")
-	 (eq_attr "type1" "alu_reg1,alu_regx,lea,moveq_l,mul_l,mul_w")
-	 (const_string "reg")
-	 (eq_attr "type1" "pea") (const_string "mem1")
-	 (eq_attr "type1" "bcc") (const_string "imm_q")
-	 (eq_attr "type1" "bra,bsr") (const_string "imm_w")
-	 (eq_attr "type1" "jmp,jsr")
-	 (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
-	(symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
-
 ;; Type of the Y operand.
 ;; See m68k.c: enum attr_op_type.
 (define_attr "opy_type"
-  "none, reg, mem1, mem234, mem5, mem6, mem7, imm_q, imm_w, imm_l"
-  (cond [(eq_attr "type1" "alu_reg1,bcc,bra,bsr,clr,jmp,jsr,rts,tst,tst_l,
-                           unlk") (const_string "none")
-	 (eq_attr "type1" "mov3q_l,moveq_l,aluq_l") (const_string "imm_q")
-	 (eq_attr "type1" "lea,pea")
+  "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
+  (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore,
+                          jmp,jsr,nop,rts,scc,trap,tst,tst_l,
+                          unlk,unknown") (const_string "none")
+	 (eq_attr "type" "lea,pea")
 	 (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")]
 	(symbol_ref "m68k_sched_attr_opy_type (insn, 0)")))
 
-;; Instruction size in words.
-(define_attr "size" ""
-  (cond [(eq_attr "type1" "alu_reg1,moveq_l,rts,unlk") (const_int 1)]
-	(symbol_ref "m68k_sched_attr_size (insn)")))
+;; Type of the X operand.
+;; See m68k.c: enum attr_op_type.
+(define_attr "opx_type"
+  "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
+  (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
+                          unknown") (const_string "none")
+	 (eq_attr "type" "pea") (const_string "mem1")
+	 (eq_attr "type" "jmp,jsr")
+	 (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
+	(symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
 
 ;; Access to the X operand: none, read, write, read/write, unknown.
 ;; Access to the Y operand is either none (if opy_type is none)
 ;; or read otherwise.
-(define_attr "opx_access" "none, r, w, rw, unknown"
-  (cond [(eq_attr "type1" "rts,unlk") (const_string "none")
-	 (eq_attr "type1" "bcc,bra,bsr,cmp_l,jmp,jsr,tst,tst_l")
-	 (const_string "r")
-	 (eq_attr "type1" "clr,lea,mov3q_l,move,move_l,moveq_l,pea")
-	 (const_string "w")
-	 (eq_attr "type1" "alu_l,alu_reg1,alu_regx,aluq_l")
-	 (const_string "rw")]
-	(const_string "unknown")))
-
-;; Memory relation of operands:
-;; r - register or immediate operand
-;; m - non-indexed memory location
-;; i - indexed memory location
-
-(define_attr "opx_mem" "r, m, i, unknown"
-  (cond [(eq_attr "opx_type" "none,reg,imm_q,imm_w,imm_l") (const_string "r")
-	 (eq_attr "opx_type" "mem1,mem234,mem5,mem7") (const_string "m")
-	 (eq_attr "opx_type" "mem6") (const_string "i")]
-	(const_string "unknown")))
-
-(define_attr "opy_mem" "r, m, i, unknown"
-  (cond [(eq_attr "opy_type" "none,reg,imm_q,imm_w,imm_l") (const_string "r")
-	 (eq_attr "opy_type" "mem1,mem234,mem5,mem7") (const_string "m")
-	 (eq_attr "opy_type" "mem6") (const_string "i")]
-	(const_string "unknown")))
+(define_attr "opx_access" "none, r, w, rw"
+  (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
+                          unknown") (const_string "none")
+	 (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst,
+                          jmp,jsr,tst,tst_l") (const_string "r")
+	 (eq_attr "type" "clr,clr_l,fneg,fmove,lea,
+                          mov3q_l,move,move_l,moveq_l,mvsz,
+                          pea,scc") (const_string "w")
+	 (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext,
+                          falu,fdiv,fmul,fsqrt,link,mul_w,mul_l,
+                          neg_l,shift") (const_string "rw")]
+	;; Should never be used.
+	(symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)")))
 
 ;; Memory accesses of the insn.
 ;; 00 - no memory references
 ;; 10 - memory is read
-;; i10 - indexed memory is read
+;; i0 - indexed memory is read
 ;; 01 - memory is written
-;; 0i1 - indexed memory is written
+;; 0i - indexed memory is written
 ;; 11 - memory is read, memory is written
-;; i11 - indexed memory is read, memory is written
-;; 1i1 - memory is read, indexed memory is written
-;;
-;; unknown - should now occur on normal insn.
-;; ??? This attribute is implemented in C to spare genattrtab from
-;; ??? optimizing it.
-(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i, unknown"
-;  (cond [(and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "r"))
-;	 (const_string "00")
-;
-;	 (and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "m"))
-;	 (cond [(eq_attr "opx_access" "r") (const_string "10")
-;	        (eq_attr "opx_access" "w") (const_string "01")
-;	        (eq_attr "opx_access" "rw") (const_string "11")]
-;	       (const_string "unknown"))
-;
-;	 (and (eq_attr "opy_mem" "r") (eq_attr "opx_mem" "i"))
-;	 (cond [(eq_attr "opx_access" "r") (const_string "i0")
-;	        (eq_attr "opx_access" "w") (const_string "0i")
-;		(eq_attr "opx_access" "rw") (const_string "i1")]
-;	       (const_string "unknown"))
-;
-;	 (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "r"))
-;	 (const_string "10")
-;
-;	 (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "m"))
-;	 (cond [(eq_attr "opx_access" "w") (const_string "11")]
-;	       (const_string "unknown"))
-;
-;	 (and (eq_attr "opy_mem" "m") (eq_attr "opx_mem" "i"))
-;	 (cond [(eq_attr "opx_access" "w") (const_string "1i")]
-;	       (const_string "unknown"))
-;
-;	 (and (eq_attr "opy_mem" "i") (eq_attr "opx_mem" "r"))
-;	 (const_string "i0")
-;
-;	 (and (eq_attr "opy_mem" "i") (eq_attr "opx_mem" "m"))
-;	 (cond [(eq_attr "opx_access" "w") (const_string "i1")]
-;	       (const_string "unknown"))]
-;	(const_string "unknown"))
+;; i1 - indexed memory is read, memory is written
+;; 1i - memory is read, indexed memory is written
+(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i"
   (symbol_ref "m68k_sched_attr_op_mem (insn)"))
 
-;; Attribute to support partial automata description.
-;; This attribute has value 'yes' for instructions that are not
-;; fully handled yet.
-(define_attr "guess" "yes, no"
-  (cond [(ior (eq (symbol_ref "reload_completed") (const_int 0))
-	      (eq_attr "type1" "unknown"))
-	 (const_string "yes")]
-	(const_string "no")))
-
-;; Attribute to support statistics gathering.
-;; Todo means that insn lacks something to get pipeline description.
-;; Done means that insn was transformed to suit pipeline description.
-;; Nothing means that insn was originally good enough for scheduling. 
-(define_attr "split" "todo, done, nothing"
-  (if_then_else (eq_attr "type" "unknown")
-		(const_string "todo")
-		(const_string "nothing")))
+;; Instruction size in words.
+(define_attr "size" "1,2,3"
+  (symbol_ref "m68k_sched_attr_size (insn)"))
+
 
 ;; Mode macros for floating point operations.
 ;; Valid floating point modes
@@ -369,8 +272,7 @@
   m68k_emit_move_double (operands);
   DONE;
 }
-  [(set_attr "type" "fmove,*")
-   (set_attr "split" "done,*")])
+  [(set_attr "type" "fmove,*")])
 
 (define_insn_and_split "pushdi"
   [(set (match_operand:DI 0 "push_operand" "=m")
@@ -450,7 +352,7 @@
   "@
    tst%.l %0
    cmp%.w #0,%0"
-  [(set_attr "type" "tst_l,*")])
+  [(set_attr "type" "tst_l,cmp")])
 
 ;; This can't use an address register, because comparisons
 ;; with address registers as second operand always test the whole word.
@@ -465,7 +367,7 @@
 	(match_operand:HI 0 "nonimmediate_operand" "dm"))]
   ""
   "tst%.w %0"
-  [(set_attr "type" "tst_w")])
+  [(set_attr "type" "tst")])
 
 (define_expand "tstqi"
   [(set (cc0)
@@ -478,7 +380,7 @@
 	(match_operand:QI 0 "nonimmediate_operand" "dm"))]
   ""
   "tst%.b %0"
-  [(set_attr "type" "tst_b")])
+  [(set_attr "type" "tst")])
 
 (define_expand "tst<mode>"
   [(set (cc0)
@@ -497,7 +399,8 @@
   if (FP_REG_P (operands[0]))
     return "ftst%.x %0";
   return "ftst%.<FP:prec> %0";
-})
+}
+  [(set_attr "type" "ftst")])
 
 (define_insn "tst<mode>_cf"
   [(set (cc0)
@@ -605,7 +508,7 @@
   if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
       || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
     {
-      cc_status.flags |= CC_REVERSED;
+      cc_status.flags |= CC_REVERSED; /*|*/
       return "cmp%.w %d0,%d1";
     }
   return "cmp%.w %d1,%d0";
@@ -797,8 +700,7 @@
    clr%.l %0
    mov3q%.l %1,%-
    pea %a1"
-  [(set_attr "type" "clr_l,mov3q_l,pea")
-   (set_attr "split" "done")])
+  [(set_attr "type" "clr_l,mov3q_l,pea")])
 
 ;This is never used.
 ;(define_insn "swapsi"
@@ -818,9 +720,8 @@
    moveq #0,%0
    sub%.l %0,%0
    clr%.l %0"
-  [(set_attr "type" "moveq_l,sub_l,clr_l")
-   (set_attr "opy_type" "imm_q,reg,*")
-   (set_attr "split" "done")])
+  [(set_attr "type" "moveq_l,alu_l,clr_l")
+   (set_attr "opy" "*,0,*")])
 
 ;; Special case of fullword move when source is zero for 68040_60.
 ;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1
@@ -839,9 +740,7 @@
       return "";
     }
 }
-  [(set_attr "type" "lea,clr_l")
-   (set_attr "opy_type" "imm_w,*")
-   (set_attr "split" "done")])
+  [(set_attr "type" "lea,clr_l")])
 
 ;; Special case of fullword move when source is zero.
 (define_insn "*movsi_const0"
@@ -851,9 +750,8 @@
   "@
    sub%.l %0,%0
    clr%.l %0"
-  [(set_attr "type" "sub_l,clr_l")
-   (set_attr "opy_type" "reg,*")
-   (set_attr "split" "done")])
+  [(set_attr "type" "alu_l,clr_l")
+   (set_attr "opy" "0,*")])
 
 ;; General case of fullword move.
 ;;
@@ -978,11 +876,7 @@
       return "";
     }
 }
-  [(set_attr "type" "mov3q_l, moveq_l,*, mvz_w, mvs_w, move_l, move_w, pea, lea, move_l, move_l, move_l")
-   (set (attr "split")
-	(if_then_else (eq_attr "alternative" "2")
-		      (const_string "*")
-		      (const_string "done")))])
+  [(set_attr "type" "mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")])
 
 ;; Special case of fullword move, where we need to get a non-GOT PIC
 ;; reference into an address register.
@@ -1071,8 +965,7 @@
    clr%.b %0
    move%.b %1,%0
    move%.b %1,%0"
-  [(set_attr "type" "clr_b,clr_b,move_b,move_b")
-   (set_attr "split" "done")])
+  [(set_attr "type" "clr,clr,move,move")])
 
 (define_expand "pushqi1"
   [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
@@ -1693,7 +1586,7 @@
 	(zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
   "ISA_HAS_MVS_MVZ"
   "mvz%.w %1,%0"
-  [(set_attr "type" "mvz_w")])
+  [(set_attr "type" "mvsz")])
 
 (define_insn "zero_extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -1718,7 +1611,7 @@
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
   "ISA_HAS_MVS_MVZ"
   "mvz%.b %1,%0"
-  [(set_attr "type" "mvz_b")])
+  [(set_attr "type" "mvsz")])
 
 (define_insn "zero_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -1871,7 +1764,7 @@
 	 (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
   "ISA_HAS_MVS_MVZ"
   "mvs%.w %1,%0"
-  [(set_attr "type" "mvs_w")])
+  [(set_attr "type" "mvsz")])
 
 (define_insn "*68k_extendhisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
@@ -1881,14 +1774,14 @@
   "@
    ext%.l %0
    move%.w %1,%0"
-  [(set_attr "type" "ext_l,move_w")])
+  [(set_attr "type" "ext,move")])
 
 (define_insn "extendqihi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
 	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
   ""
   "ext%.w %0"
-  [(set_attr "type" "ext_w")])
+  [(set_attr "type" "ext")])
 
 (define_expand "extendqisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -1901,14 +1794,14 @@
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
   "ISA_HAS_MVS_MVZ"
   "mvs%.b %1,%0"
-  [(set_attr "type" "mvs_b")])
+  [(set_attr "type" "mvsz")])
 
 (define_insn "*68k_extendqisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
   "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)"
   "extb%.l %0"
-  [(set_attr "type" "extb_l")])
+  [(set_attr "type" "ext")])
 
 ;; Conversions between float and double.
 
@@ -2026,7 +1919,8 @@
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
 	(float:FP (match_operand:SI 1 "general_operand" "dmi")))]
   "TARGET_68881"
-  "f<FP:round>move%.l %1,%0")
+  "f<FP:round>move%.l %1,%0"
+  [(set_attr "type" "fmove")])
 
 (define_insn "floatsi<mode>2_cf"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
@@ -2133,7 +2027,8 @@
   if (FP_REG_P (operands[1]))
     return "fintrz%.x %f1,%0";
   return "fintrz%.<FP:prec> %f1,%0";
-})
+}
+  [(set_attr "type" "falu")])
 
 (define_insn "ftrunc<mode>2_cf"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
@@ -2144,7 +2039,7 @@
     return "fintrz%.d %f1,%0";
   return "fintrz%.<FP:prec> %f1,%0";
 }
-  [(set_attr "type" "fintrz")])
+  [(set_attr "type" "falu")])
 
 ;; Convert a float whose value is an integer
 ;; to an actual integer.  Second stage of converting float to integer type.
@@ -2158,7 +2053,8 @@
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
 	(fix:QI (match_operand:FP 1 "general_operand" "f")))]
   "TARGET_68881"
-  "fmove%.b %1,%0")
+  "fmove%.b %1,%0"
+  [(set_attr "type" "fmove")])
 
 (define_insn "fix<mode>qi2_cf"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
@@ -2177,7 +2073,8 @@
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
 	(fix:HI (match_operand:FP 1 "general_operand" "f")))]
   "TARGET_68881"
-  "fmove%.w %1,%0")
+  "fmove%.w %1,%0"
+  [(set_attr "type" "fmove")])
 
 (define_insn "fix<mode>hi2_cf"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
@@ -2196,7 +2093,8 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
 	(fix:SI (match_operand:FP 1 "general_operand" "f")))]
   "TARGET_68881"
-  "fmove%.l %1,%0")
+  "fmove%.l %1,%0"
+  [(set_attr "type" "fmove")])
 
 (define_insn "fix<mode>si2_cf"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
@@ -2302,7 +2200,7 @@
     operands[1] = adjust_address (operands[1], SImode, 4);
   return "add%.l %1,%0";
 }
-  [(set_attr "type" "add_l")])
+  [(set_attr "type" "alu_l")])
 
 (define_insn "adddi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
@@ -2469,10 +2367,9 @@
 	(plus:SI (match_dup 0)
 		 (match_dup 1)))]
   ""
-  [(set_attr "type" "addq_l,subq_l,add_l,add_l,*,lea,lea,lea")
+  [(set_attr "type" "aluq_l,aluq_l,alu_l,alu_l,*,lea,lea,lea")
    (set_attr "opy" "2,2,2,2,*,*,*,*")
-   (set_attr "opy_type" "*,*,*,*,*,mem6,mem6,mem5")
-   (set_attr "split" "done,done,done,done,*,done,done,done")])
+   (set_attr "opy_type" "*,*,*,*,*,mem6,mem6,mem5")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
@@ -2716,21 +2613,27 @@
 	(plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
 		 (match_operand:FP 1 "general_operand" "0")))]
   "TARGET_68881"
-  "f<FP:round>add%.l %2,%0")
+  "f<FP:round>add%.l %2,%0"
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 (define_insn "add<mode>3_floathi_68881"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
 	(plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
 		 (match_operand:FP 1 "general_operand" "0")))]
   "TARGET_68881"
-  "f<FP:round>add%.w %2,%0")
+  "f<FP:round>add%.w %2,%0"
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 (define_insn "add<mode>3_floatqi_68881"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
 	(plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
 		 (match_operand:FP 1 "general_operand" "0")))]
   "TARGET_68881"
-  "f<FP:round>add%.b %2,%0")
+  "f<FP:round>add%.b %2,%0"
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 (define_insn "add<mode>3_68881"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
@@ -2741,7 +2644,9 @@
   if (FP_REG_P (operands[2]))
     return "f<FP:round>add%.x %2,%0";
   return "f<FP:round>add%.<FP:prec> %f2,%0";
-})
+}
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 (define_insn "add<mode>3_cf"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
@@ -2753,7 +2658,8 @@
     return "f<FP:prec>add%.d %2,%0";
   return "f<FP:prec>add%.<FP:prec> %2,%0";
 }
-  [(set_attr "type" "fadd")])
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 ;; subtract instructions
 
@@ -2788,7 +2694,7 @@
     operands[1] = adjust_address (operands[1], SImode, 4);
   return "sub%.l %1,%0";
 }
-  [(set_attr "type" "sub_l")])
+  [(set_attr "type" "alu_l")])
 
 (define_insn "subdi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
@@ -2879,7 +2785,7 @@
    sub%.l %2,%0
    sub%.l %2,%0
    sub%.l %2,%0"
-  [(set_attr "type" "subq_l,sub_l,sub_l,sub_l")
+  [(set_attr "type" "aluq_l,alu_l,alu_l,alu_l")
    (set_attr "opy" "2")])
 
 (define_insn ""
@@ -2930,21 +2836,27 @@
 	(minus:FP (match_operand:FP 1 "general_operand" "0")
 		  (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
   "TARGET_68881"
-  "f<FP:round>sub%.l %2,%0")
+  "f<FP:round>sub%.l %2,%0"
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 (define_insn "sub<mode>3_floathi_68881"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
 	(minus:FP (match_operand:FP 1 "general_operand" "0")
 		  (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
   "TARGET_68881"
-  "f<FP:round>sub%.w %2,%0")
+  "f<FP:round>sub%.w %2,%0"
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 (define_insn "sub<mode>3_floatqi_68881"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
 	(minus:FP (match_operand:FP 1 "general_operand" "0")
 		  (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
   "TARGET_68881"
-  "f<FP:round>sub%.b %2,%0")
+  "f<FP:round>sub%.b %2,%0"
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 (define_insn "sub<mode>3_68881"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
@@ -2955,7 +2867,9 @@
   if (FP_REG_P (operands[2]))
     return "f<FP:round>sub%.x %2,%0";
   return "f<FP:round>sub%.<FP:prec> %f2,%0";
-})
+}
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 (define_insn "sub<mode>3_cf"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
@@ -2967,7 +2881,8 @@
     return "f<FP:prec>sub%.d %2,%0";
   return "f<FP:prec>sub%.<FP:prec> %2,%0";
 }
-  [(set_attr "type" "fsub")])
+  [(set_attr "type" "falu")
+   (set_attr "opy" "2")])
 
 ;; multiply instructions
 
@@ -2979,7 +2894,7 @@
 {
   return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
 }
-  [(set_attr "type" "muls_w")
+  [(set_attr "type" "mul_w")
    (set_attr "opy" "2")])
 
 (define_insn "mulhisi3"
@@ -2992,7 +2907,7 @@
 {
   return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
 }
-  [(set_attr "type" "muls_w")
+  [(set_attr "type" "mul_w")
    (set_attr "opy" "2")])
 
 (define_insn "*mulhisisi3_s"
@@ -3004,7 +2919,7 @@
 {
   return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
 }
-  [(set_attr "type" "muls_w")
+  [(set_attr "type" "mul_w")
    (set_attr "opy" "2")])
 
 (define_expand "mulsi3"
@@ -3021,7 +2936,7 @@
 
   "TARGET_68020"
   "muls%.l %2,%0"
-  [(set_attr "type" "muls_l")
+  [(set_attr "type" "mul_l")
    (set_attr "opy" "2")])
 
 (define_insn "*mulsi3_cf"
@@ -3030,7 +2945,7 @@
 		 (match_operand:SI 2 "general_operand" "d<Q>")))]
   "TARGET_COLDFIRE"
   "muls%.l %2,%0"
-  [(set_attr "type" "muls_l")
+  [(set_attr "type" "mul_l")
    (set_attr "opy" "2")])
 
 (define_insn "umulhisi3"
@@ -3043,7 +2958,7 @@
 {
   return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
 }
-  [(set_attr "type" "mulu_w")
+  [(set_attr "type" "mul_w")
    (set_attr "opy" "2")])
 
 (define_insn "*mulhisisi3_z"
@@ -3055,7 +2970,7 @@
 {
   return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
 }
-  [(set_attr "type" "mulu_w")
+  [(set_attr "type" "mul_w")
    (set_attr "opy" "2")])
 
 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
@@ -3240,7 +3155,9 @@
   return TARGET_68040
 	 ? "f<FP:round>mul%.l %2,%0"
 	 : "f<FP:round_mul>mul%.l %2,%0";
-})
+}
+  [(set_attr "type" "fmul")
+   (set_attr "opy" "2")])
 
 (define_insn "mul<mode>3_floathi_68881"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
@@ -3251,7 +3168,9 @@
   return TARGET_68040
 	 ? "f<FP:round>mul%.w %2,%0"
 	 : "f<FP:round_mul>mul%.w %2,%0";
-})
+}
+  [(set_attr "type" "fmul")
+   (set_attr "opy" "2")])
 
 (define_insn "mul<mode>3_floatqi_68881"
   [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
@@ -3262,7 +3181,9 @@
   return TARGET_68040
 	 ? "f<FP:round>mul%.b %2,%0"
 	 : "f<FP:round_mul>mul%.b %2,%0";
-})
+}
+  [(set_attr "type" "fmul")
+   (set_attr "opy" "2")])
 
 (define_insn "muldf_68881"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
@@ -3316,7 +3237,8 @@
     return "f<FP:prec>mul%.d %2,%0";
   return "f<FP:prec>mul%.<FP:prec> %2,%0";
 }
-  [(set_attr "type" "fmul")])
+  [(set_attr "type" "fmul")
+   (set_attr "opy" "2")])
 
 ;; divide instructions
 
@@ -3385,7 +3307,8 @@
     return "f<FP:prec>div%.d %2,%0";
   return "f<FP:prec>div%.<FP:prec> %2,%0";
 }
-  [(set_attr "type" "fdiv")])
+  [(set_attr "type" "fdiv")
+   (set_attr "opy" "2")])
 
 ;; Remainder instructions.
 
@@ -3413,7 +3336,9 @@
     return "rems%.l %2,%3:%0";
   else
     return "rems%.l %2,%3:%0\;divs%.l %2,%0";
-})
+}
+  [(set_attr "type" "div_l")
+   (set_attr "opy" "2")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
@@ -3453,7 +3378,9 @@
     return "remu%.l %2,%3:%0";
   else
     return "remu%.l %2,%3:%0\;divu%.l %2,%0";
-})
+}
+  [(set_attr "type" "div_l")
+   (set_attr "opy" "2")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
@@ -4261,7 +4188,8 @@
   if (FP_REG_P (operands[1]))
     return "f<FP:prec>sqrt%.d %1,%0";
   return "f<FP:prec>sqrt%.<FP:prec> %1,%0";
-})
+}
+  [(set_attr "type" "fsqrt")])
 ;; Absolute value instructions
 ;; If using software floating point, just zero the sign bit.
 
@@ -4384,7 +4312,8 @@
   if (FP_REG_P (operands[1]))
     return "f<FP:prec>abs%.d %1,%0";
   return "f<FP:prec>abs%.<FP:prec> %1,%0";
-})
+}
+  [(set_attr "type" "bitrw,fneg")])
 
 ;; bit indexing instructions
 
@@ -4394,7 +4323,7 @@
  	(clz:SI (match_operand:SI 1 "register_operand" "0")))]
   "ISA_HAS_FF1"
   "ff1 %0"
-  [(set_attr "type" "ff1")])
+  [(set_attr "type" "ext")])
 
 ;; one complement instructions
 
@@ -4438,7 +4367,7 @@
 	(not:SI (match_operand:SI 1 "general_operand" "0")))]
   "TARGET_COLDFIRE"
   "not%.l %0"
-  [(set_attr "type" "not_l")])
+  [(set_attr "type" "neg_l")])
 
 (define_insn "one_cmplhi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
@@ -4790,7 +4719,7 @@
     operands[1] = adjust_address (operands[1], HImode, 2);
   return "move%.w %1,%0";
 }
-  [(set_attr "type" "move_w")])
+  [(set_attr "type" "move")])
 
 (define_insn "subregsi1ashrdi_const32"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
@@ -4970,7 +4899,7 @@
 		     (match_operand:SI 2 "general_operand" "dI")))]
   ""
   "asr%.l %2,%0"
-  [(set_attr "type" "asr_l")
+  [(set_attr "type" "shift")
    (set_attr "opy" "2")])
 
 (define_insn "ashrhi3"
@@ -5266,7 +5195,7 @@
 		     (match_operand:SI 2 "general_operand" "dI")))]
   ""
   "lsr%.l %2,%0"
-  [(set_attr "type" "lsr_l")
+  [(set_attr "type" "shift")
    (set_attr "opy" "2")])
 
 (define_insn "lshrhi3"
@@ -5425,7 +5354,7 @@
   CC_STATUS_INIT;
   return "bset %1,%0";
 }
-  [(set_attr "type" "bset")])
+  [(set_attr "type" "bitrw")])
 
 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
 (define_insn "*bsetmemqi_ext"
@@ -5439,7 +5368,7 @@
   CC_STATUS_INIT;
   return "bset %1,%0";
 }
-  [(set_attr "type" "bset")])
+  [(set_attr "type" "bitrw")])
 
 ;; clear bit, bit number is int
 (define_insn "bclrmemqi"
@@ -5453,7 +5382,7 @@
   CC_STATUS_INIT;
   return "bclr %1,%0";
 }
-  [(set_attr "type" "bclr")])
+  [(set_attr "type" "bitrw")])
 
 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
 (define_insn "*bclrmemqi_ext"
@@ -5468,7 +5397,7 @@
   CC_STATUS_INIT;
   return "bclr %1,%0";
 }
-  [(set_attr "type" "bclr")])
+  [(set_attr "type" "bitrw")])
 
 ;; Special cases of bit-field insns which we should
 ;; recognize in preference to the general case.
@@ -6418,8 +6347,7 @@
 {
   OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
 }
-  [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
-   (set_attr "split" "done")])
+  [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
 
 (define_insn "bne"
   [(set (pc)
@@ -6431,8 +6359,7 @@
 {
   OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
 }
-  [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
-   (set_attr "split" "done")])
+  [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
 
 (define_insn "bgt"
   [(set (pc)
@@ -6444,8 +6371,7 @@
 {
   OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
 }
-  [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
-   (set_attr "split" "done")])
+  [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
 
 (define_insn "bgtu"
   [(set (pc)
@@ -6467,8 +6393,7 @@
 {
   OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
 }
-  [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))
-   (set_attr "split" "done")])
+  [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
 
 (define_insn "bltu"
   [(set (pc)
@@ -6532,7 +6457,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjor %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "bunordered"
   [(set (pc)
@@ -6543,7 +6469,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjun %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "buneq"
   [(set (pc)
@@ -6554,7 +6481,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjueq %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "bunge"
   [(set (pc)
@@ -6565,7 +6493,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjuge %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "bungt"
   [(set (pc)
@@ -6576,7 +6505,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjugt %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "bunle"
   [(set (pc)
@@ -6587,7 +6517,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjule %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "bunlt"
   [(set (pc)
@@ -6598,7 +6529,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjult %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "bltgt"
   [(set (pc)
@@ -6609,7 +6541,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjogl %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 ;; Negated conditional jump instructions.
 
@@ -6734,7 +6667,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjun %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "*bunordered_rev"
   [(set (pc)
@@ -6745,7 +6679,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjor %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "*buneq_rev"
   [(set (pc)
@@ -6756,7 +6691,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjogl %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "*bunge_rev"
   [(set (pc)
@@ -6767,7 +6703,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjolt %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "*bungt_rev"
   [(set (pc)
@@ -6778,7 +6715,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjole %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "*bunle_rev"
   [(set (pc)
@@ -6789,7 +6727,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjogt %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "*bunlt_rev"
   [(set (pc)
@@ -6800,7 +6739,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjoge %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 (define_insn "*bltgt_rev"
   [(set (pc)
@@ -6811,7 +6751,8 @@
 {
   gcc_assert (cc_prev_status.flags & CC_IN_68881);
   return "fjueq %l0";
-})
+}
+  [(set_attr "type" "fbcc")])
 
 ;; Unconditional and other jump instructions
 (define_insn "jump"
@@ -6840,7 +6781,7 @@
 {
   return MOTOROLA ? "jmp (%0)" : "jmp %0@";
 }
-  [(set_attr "type" "bra")])
+  [(set_attr "type" "jmp")])
 
 ;; Jump to variable address from dispatch table of relative addresses.
 (define_insn ""
@@ -7018,7 +6959,8 @@
   "!SIBLING_CALL_P (insn)"
 {
   return output_call (operands[0]);
-})
+}
+  [(set_attr "type" "jsr")])
 
 ;; Call subroutine, returning value in operand 0
 ;; (which must be a hard register).
@@ -7040,7 +6982,6 @@
   "!SIBLING_CALL_P (insn)"
   "jsr %a1"
   [(set_attr "type" "jsr")
-   (set_attr "split" "done")
    (set_attr "opx" "1")])
 
 (define_insn "*symbolic_call_value_jsr"
@@ -7054,7 +6995,6 @@
   return m68k_symbolic_call;
 }
   [(set_attr "type" "jsr")
-   (set_attr "split" "done")
    (set_attr "opx" "1")])
 
 (define_insn "*symbolic_call_value_bsr"
@@ -7070,7 +7010,6 @@
   return m68k_symbolic_call;
 }
   [(set_attr "type" "bsr")
-   (set_attr "split" "done")
    (set_attr "opx" "1")])
 
 ;; Call subroutine returning any type.
@@ -7236,7 +7175,8 @@
     return "link.w %0,%1";
   else
     return "link.l %0,%1";
-})
+}
+  [(set_attr "type" "link")])
 
 (define_expand "unlink"
   [(parallel
@@ -7726,6 +7666,17 @@
   }
 })
 
+;; These are to prevent the scheduler from moving stores to the frame
+;; before the stack adjustment.
+(define_insn "stack_tie"
+  [(set (mem:BLK (scratch))
+	(unspec:BLK [(match_operand:SI 0 "register_operand" "r")
+		     (match_operand:SI 1 "register_operand" "r")]
+		    UNSPEC_TIE))]
+  ""
+  ""
+  [(set_attr "type" "ignore")])
+
 ;; Instruction that subscribes one word in ColdFire instruction buffer.
 ;; This instruction is used within scheduler only and should not appear
 ;; in the instruction stream.