Add prototype header file

Import some code from Cygnus internal sources.

From-SVN: r30459

4 files changed, 1941 insertions, 689 deletions

diff --git a/gcc/config/m32r/m32r-protos.h b/gcc/config/m32r/m32r-protos.h
new file mode 100644
index 0000000..d6bd9ae
--- /dev/null
+++ b/gcc/config/m32r/m32r-protos.h
@@ -0,0 +1,110 @@
+/* Prototypes for m32r.c functions used in the md file & elsewhere.
+   Copyright (C) 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Function prototypes that cannot exist in v850.h due to dependency
+   compilcations.  */
+#define Mmode enum machine_mode
+
+extern void   sbss_section			PROTO ((void));
+extern void   sdata_section			PROTO ((void));
+extern void   m32r_init				PROTO ((void));
+extern void   m32r_init_expanders		PROTO ((void));
+extern unsigned m32r_compute_frame_size		PROTO ((int));
+extern int    m32r_first_insn_address		PROTO ((void));
+extern void   m32r_expand_prologue		PROTO ((void));
+extern void   m32r_output_function_prologue	PROTO ((FILE *, int));
+extern void   m32r_output_function_epilogue	PROTO ((FILE *, int));
+extern void   m32r_finalize_pic			PROTO ((void));
+extern void   m32r_asm_file_start		PROTO ((FILE *));
+extern void   m32r_sched_init 			PROTO ((FILE *, int));
+extern int    direct_return 			PROTO ((void));
+#ifdef TREE_CODE
+extern int    m32r_valid_machine_decl_attribute	PROTO ((tree, tree, tree, tree));
+extern int    m32r_comp_type_attributes		PROTO ((tree, tree));
+extern void   m32r_select_section		PROTO ((tree, int));
+extern void   m32r_encode_section_info		PROTO ((tree));
+extern enum m32r_function_type m32r_compute_function_type PROTO ((tree));
+extern void   m32r_select_section 		PROTO ((tree, int));
+extern void   m32r_set_default_type_attributes  PROTO ((tree));
+
+#ifdef HAVE_MACHINE_MODES
+extern void   m32r_setup_incoming_varargs	PROTO ((CUMULATIVE_ARGS *, Mmode, tree, int *, int));
+extern int    function_arg_partial_nregs	PROTO ((CUMULATIVE_ARGS *, Mmode, tree, int));
+#endif
+#endif /* TREE_CODE */
+
+#ifdef RTX_CODE
+extern int    easy_di_const			PROTO ((rtx));
+extern int    easy_df_const			PROTO ((rtx));
+extern int    m32r_select_cc_mode		PROTO ((int, rtx, rtx));
+extern rtx    gen_compare			PROTO ((enum rtx_code, rtx, rtx, int));
+extern rtx    gen_split_move_double		PROTO ((rtx *));
+extern int    m32r_address_code			PROTO ((rtx));
+extern void   m32r_initialize_trampoline	PROTO ((rtx, rtx, rtx));
+extern int    zero_and_one			PROTO ((rtx, rtx));
+extern char * emit_cond_move			PROTO ((rtx *, rtx));
+extern char * m32r_output_block_move 		PROTO ((rtx, rtx *));
+extern void   m32r_expand_block_move 		PROTO ((rtx *));
+extern void   m32r_print_operand		PROTO ((FILE *, rtx, int));
+extern void   m32r_print_operand_address	PROTO ((FILE *, rtx));
+extern int    m32r_address_cost 		PROTO ((rtx));
+extern int    m32r_adjust_cost 			PROTO ((rtx, rtx, rtx, int));
+extern int    m32r_adjust_priority 		PROTO ((rtx, int));
+extern void   m32r_sched_reorder 		PROTO ((FILE *, int, rtx *, int));
+extern int    m32r_sched_variable_issue 	PROTO ((FILE *, int, rtx, int));
+extern int    m32r_not_same_reg 		PROTO ((rtx, rtx));
+
+#ifdef HAVE_MACHINE_MODES
+extern int    call_address_operand		PROTO ((rtx, Mmode));
+extern int    call_operand			PROTO ((rtx, Mmode));
+extern int    symbolic_operand			PROTO ((rtx, Mmode));
+extern int    small_data_operand		PROTO ((rtx, Mmode));
+extern int    addr24_operand			PROTO ((rtx, Mmode));
+extern int    addr32_operand			PROTO ((rtx, Mmode));
+extern int    call26_operand			PROTO ((rtx, Mmode));
+extern int    seth_add3_operand			PROTO ((rtx, Mmode));
+extern int    cmp_int16_operand			PROTO ((rtx, Mmode));
+extern int    uint16_operand			PROTO ((rtx, Mmode));
+extern int    reg_or_int16_operand		PROTO ((rtx, Mmode));
+extern int    reg_or_uint16_operand		PROTO ((rtx, Mmode));
+extern int    reg_or_cmp_int16_operand		PROTO ((rtx, Mmode));
+extern int    two_insn_const_operand		PROTO ((rtx, Mmode));
+extern int    move_src_operand			PROTO ((rtx, Mmode));
+extern int    move_double_src_operand		PROTO ((rtx, Mmode));
+extern int    move_dest_operand			PROTO ((rtx, Mmode));
+extern int    eqne_comparison_operator		PROTO ((rtx, Mmode));
+extern int    signed_comparison_operator	PROTO ((rtx, Mmode));
+extern int    memreg_operand			PROTO ((rtx, Mmode));
+extern int    small_insn_p			PROTO ((rtx, Mmode));
+extern int    large_insn_p			PROTO ((rtx, Mmode));
+extern int    conditional_move_operand		PROTO ((rtx, Mmode));
+extern int    carry_compare_operand		PROTO ((rtx, Mmode));
+extern int    m32r_block_immediate_operand 	PROTO ((rtx, Mmode));
+extern int    extend_operand			PROTO ((rtx, Mmode));
+extern int    reg_or_eq_int16_operand		PROTO ((rtx, Mmode));
+extern int    int8_operand			PROTO ((rtx, Mmode));
+#endif /* HAVE_MACHINE_MODES */
+
+#ifdef TREE_CODE
+extern struct rtx_def * m32r_va_arg		PROTO ((tree, tree));
+#endif /* TREE_CODE */
+#endif /* RTX_CODE */
+
+#undef  Mmode
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 4b23157..f547332 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -35,6 +35,7 @@ Boston, MA 02111-1307, USA.  */
 #include "function.h"
 #include "recog.h"
 #include "toplev.h"
+#include "m32r-protos.h"
 
 /* Save the operands last given to a compare for use when we
    generate a scc or bcc insn.  */
@@ -44,16 +45,18 @@ rtx m32r_compare_op0, m32r_compare_op1;
 char m32r_punct_chars[256];
 
 /* Selected code model.  */
-char *m32r_model_string = M32R_MODEL_DEFAULT;
+const char * m32r_model_string = M32R_MODEL_DEFAULT;
 enum m32r_model m32r_model;
 
 /* Selected SDA support.  */
-char *m32r_sdata_string = M32R_SDATA_DEFAULT;
+const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
 enum m32r_sdata m32r_sdata;
 
+/* Scheduler support */
+int m32r_sched_odd_word_p;
 
 /* Forward declaration.  */
-static void init_reg_tables	PROTO((void));
+static void init_reg_tables			PROTO ((void));
 
 /* Called by OVERRIDE_OPTIONS to initialize various things.  */
 
@@ -88,7 +91,6 @@ m32r_init ()
     m32r_sdata = M32R_SDATA_USE;
   else
     error ("bad value (%s) for -msdata switch", m32r_sdata_string);
-
 }
 
 /* Vectors to keep interesting information about registers where it can easily
@@ -104,7 +106,7 @@ enum m32r_mode_class
 {
   C_MODE,
   S_MODE, D_MODE, T_MODE, O_MODE,
-  SF_MODE, DF_MODE, TF_MODE, OF_MODE
+  SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
 };
 
 /* Modes for condition codes.  */
@@ -119,6 +121,8 @@ enum m32r_mode_class
 /* Modes for quad-word and smaller quantities.  */
 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
 
+/* Modes for accumulators.  */
+#define A_MODES (1 << (int) A_MODE)
 
 /* Value is 1 if register/mode pair is acceptable on arc.  */
 
@@ -126,7 +130,7 @@ unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
 {
   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
-  S_MODES, C_MODES
+  S_MODES, C_MODES, A_MODES
 };
 
 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
@@ -451,23 +455,21 @@ m32r_init_expanders ()
 /* Acceptable arguments to the call insn.  */
 
 int
-call_address_operand (op, int_mode)
+call_address_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
-  return symbolic_operand (op, int_mode);
+  return symbolic_operand (op, mode);
 
 /* Constants and values in registers are not OK, because
    the m32r BL instruction can only support PC relative branching.  */ 
 }
 
 int
-call_operand (op, int_mode)
+call_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
   if (GET_CODE (op) != MEM)
     return 0;
   op = XEXP (op, 0);
@@ -477,9 +479,9 @@ call_operand (op, int_mode)
 /* Returns 1 if OP is a symbol reference.  */
 
 int
-symbolic_operand (op, int_mode)
+symbolic_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   switch (GET_CODE (op))
     {
@@ -496,9 +498,9 @@ symbolic_operand (op, int_mode)
 /* Return 1 if OP is a reference to an object in .sdata/.sbss.  */
 
 int
-small_data_operand (op, int_mode)
+small_data_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (! TARGET_SDATA_USE)
     return 0;
@@ -519,9 +521,9 @@ small_data_operand (op, int_mode)
 /* Return 1 if OP is a symbol that can use 24 bit addressing.  */
 
 int
-addr24_operand (op, int_mode)
+addr24_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_CODE (op) == LABEL_REF)
     return TARGET_ADDR24;
@@ -551,24 +553,24 @@ addr24_operand (op, int_mode)
 /* Return 1 if OP is a symbol that needs 32 bit addressing.  */
 
 int
-addr32_operand (op, int_mode)
+addr32_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
   if (GET_CODE (op) == LABEL_REF)
     return TARGET_ADDR32;
 
   if (GET_CODE (op) == SYMBOL_REF)
-    return (! addr24_operand (op, int_mode)
-	    && ! small_data_operand (op, int_mode));
+    return (! addr24_operand (op, mode)
+	    && ! small_data_operand (op, mode));
 
   if (GET_CODE (op) == CONST
       && GET_CODE (XEXP (op, 0)) == PLUS
       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
     {
-      return (! addr24_operand (op, int_mode)
-	      && ! small_data_operand (op, int_mode));
+      return (! addr24_operand (op, mode)
+	      && ! small_data_operand (op, mode));
     }
 
   return 0;
@@ -577,9 +579,9 @@ addr32_operand (op, int_mode)
 /* Return 1 if OP is a function that can be called with the `bl' insn.  */
 
 int
-call26_operand (op, int_mode)
+call26_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_CODE (op) == SYMBOL_REF)
     return ! LARGE_NAME_P (XSTR (op, 0));
@@ -590,9 +592,9 @@ call26_operand (op, int_mode)
 /* Returns 1 if OP is an acceptable operand for seth/add3.  */
 
 int
-seth_add3_operand (op, int_mode)
+seth_add3_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_CODE (op) == SYMBOL_REF
       || GET_CODE (op) == LABEL_REF)
@@ -608,13 +610,25 @@ seth_add3_operand (op, int_mode)
   return 0;
 }
 
+/* Return true if OP is a signed 8 bit immediate value.  */
+
+int
+int8_operand (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return INT8_P (INTVAL (op));
+}
+
 /* Return true if OP is a signed 16 bit immediate value
    useful in comparisons.  */
 
 int
-cmp_int16_operand (op, int_mode)
+cmp_int16_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_CODE (op) != CONST_INT)
     return 0;
@@ -624,24 +638,22 @@ cmp_int16_operand (op, int_mode)
 /* Return true if OP is an unsigned 16 bit immediate value.  */
 
 int
-uint16_operand (op, int_mode)
+uint16_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_CODE (op) != CONST_INT)
     return 0;
   return UINT16_P (INTVAL (op));
 }
 
-/* Return true if OP is a register or signed 8 bit value.  */
+/* Return true if OP is a register or signed 16 bit value.  */
 
 int
-reg_or_int16_operand (op, int_mode)
+reg_or_int16_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
     return register_operand (op, mode);
   if (GET_CODE (op) != CONST_INT)
@@ -652,12 +664,10 @@ reg_or_int16_operand (op, int_mode)
 /* Return true if OP is a register or an unsigned 16 bit value.  */
 
 int
-reg_or_uint16_operand (op, int_mode)
+reg_or_uint16_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
     return register_operand (op, mode);
   if (GET_CODE (op) != CONST_INT)
@@ -665,17 +675,37 @@ reg_or_uint16_operand (op, int_mode)
   return UINT16_P (INTVAL (op));
 }
 
-/* Return true if OP is a register or signed 16 bit value for compares.  */
+/* Return true if OP is a register or an integer value that can be
+   used is SEQ/SNE.  We can use either XOR of the value or ADD of
+   the negative of the value for the constant.  Don't allow 0,
+   because that is special cased.  */
 
 int
-reg_or_cmp_int16_operand (op, int_mode)
+reg_or_eq_int16_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
+  HOST_WIDE_INT value;
 
   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
     return register_operand (op, mode);
+
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+
+  value = INTVAL (op);
+  return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
+}
+
+/* Return true if OP is a register or signed 16 bit value for compares.  */
+
+int
+reg_or_cmp_int16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+    return register_operand (op, mode);
   if (GET_CODE (op) != CONST_INT)
     return 0;
   return CMP_INT16_P (INTVAL (op));
@@ -684,9 +714,9 @@ reg_or_cmp_int16_operand (op, int_mode)
 /* Return true if OP is a const_int requiring two instructions to load.  */
 
 int
-two_insn_const_operand (op, int_mode)
+two_insn_const_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_CODE (op) != CONST_INT)
     return 0;
@@ -701,16 +731,15 @@ two_insn_const_operand (op, int_mode)
    move source.  */
 
 int
-move_src_operand (op, int_mode)
+move_src_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
   switch (GET_CODE (op))
     {
     case SYMBOL_REF :
     case CONST :
-      return addr24_operand (op, int_mode);
+      return addr24_operand (op, mode);
     case CONST_INT :
       /* ??? We allow more cse opportunities if we only allow constants
 	 loadable with one insn, and split the rest into two.  The instances
@@ -743,6 +772,9 @@ move_src_operand (op, int_mode)
       else
 	return register_operand (op, mode);
     case MEM :
+      if (GET_CODE (XEXP (op, 0)) == PRE_INC
+	  || GET_CODE (XEXP (op, 0)) == PRE_DEC)
+	return 0;		/* loads can't do pre-{inc,dec} */
       return address_operand (XEXP (op, 0), mode);
     default :
       return 0;
@@ -753,11 +785,10 @@ move_src_operand (op, int_mode)
    move source.  */
 
 int
-move_double_src_operand (op, int_mode)
+move_double_src_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
   switch (GET_CODE (op))
     {
     case CONST_INT :
@@ -769,7 +800,7 @@ move_double_src_operand (op, int_mode)
       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 	 pseudo-reg and is now a stack slot.  */
       if (GET_CODE (SUBREG_REG (op)) == MEM)
-	return move_double_src_operand (SUBREG_REG (op), int_mode);
+	return move_double_src_operand (SUBREG_REG (op), mode);
       else
 	return register_operand (op, mode);
     case MEM :
@@ -786,11 +817,10 @@ move_double_src_operand (op, int_mode)
 /* Return true if OP is an acceptable argument for a move destination.  */
 
 int
-move_dest_operand (op, int_mode)
+move_dest_operand (op, mode)
      rtx op;
-     int int_mode;
+     enum machine_mode mode;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
   switch (GET_CODE (op))
     {
     case REG :
@@ -803,6 +833,8 @@ move_dest_operand (op, int_mode)
       else
 	return register_operand (op, mode);
     case MEM :
+      if (GET_CODE (XEXP (op, 0)) == POST_INC)
+	return 0;		/* stores can't do post inc */
       return address_operand (XEXP (op, 0), mode);
     default :
       return 0;
@@ -853,9 +885,9 @@ easy_df_const (op)
 /* Return 1 if OP is an EQ or NE comparison operator.  */
 
 int
-eqne_comparison_operator (op, int_mode)
+eqne_comparison_operator (op, mode)
     rtx op;
-    int int_mode ATTRIBUTE_UNUSED;
+    enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   enum rtx_code code = GET_CODE (op);
 
@@ -867,9 +899,9 @@ eqne_comparison_operator (op, int_mode)
 /* Return 1 if OP is a signed comparison operator.  */
 
 int
-signed_comparison_operator (op, int_mode)
+signed_comparison_operator (op, mode)
     rtx op;
-    int int_mode ATTRIBUTE_UNUSED;
+    enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   enum rtx_code code = GET_CODE (op);
 
@@ -883,20 +915,48 @@ signed_comparison_operator (op, int_mode)
    This is used in insn length calcs.  */
 
 int
-memreg_operand (op, int_mode)
+memreg_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
 }
 
+/* Return true if OP is an acceptable input argument for a zero/sign extend
+   operation.  */
+
+int
+extend_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  rtx addr;
+
+  switch (GET_CODE (op))
+    {
+    case REG :
+    case SUBREG :
+      return register_operand (op, mode);
+
+    case MEM :
+      addr = XEXP (op, 0);
+      if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
+	return 0;		/* loads can't do pre inc/pre dec */
+
+      return address_operand (addr, mode);
+
+    default :
+      return 0;
+    }
+}
+
 /* Return non-zero if the operand is an insn that is a small insn.
    Allow const_int 0 as well, which is a placeholder for NOP slots.  */
 
 int
-small_insn_p (op, int_mode)
+small_insn_p (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
     return 1;
@@ -910,9 +970,9 @@ small_insn_p (op, int_mode)
 /* Return non-zero if the operand is an insn that is a large insn.  */
 
 int
-large_insn_p (op, int_mode)
+large_insn_p (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_RTX_CLASS (GET_CODE (op)) != 'i')
     return 0;
@@ -932,13 +992,13 @@ m32r_select_cc_mode (op, x, y)
      rtx x ATTRIBUTE_UNUSED;
      rtx y ATTRIBUTE_UNUSED;
 {
-  return (int)SImode;
+  return (int) CCmode;
 }
 
 /* X and Y are two things to compare using CODE.  Emit the compare insn and
    return the rtx for compare [arg0 of the if_then_else].
    If need_compare is true then the comparison insn must be generated, rather
-   than being susummed into the following branch instruction. */
+   than being susummed into the following branch instruction.  */
 
 rtx
 gen_compare (code, x, y, need_compare)
@@ -965,7 +1025,7 @@ gen_compare (code, x, y, need_compare)
     case GEU: compare_code = LTU; branch_code = EQ; break;
 
     default:
-      abort();
+      abort ();
     }
 
   if (need_compare)
@@ -992,7 +1052,7 @@ gen_compare (code, x, y, need_compare)
 	  if (register_operand (y, SImode) 		/* reg equal to reg.  */
 	      || y == const0_rtx) 	   		/* req equal to zero. */
 	    {
-		emit_insn (gen_cmp_eqsi_insn (x, y));
+	      emit_insn (gen_cmp_eqsi_insn (x, y));
 		
 	      return gen_rtx (code, mode, cc_reg, const0_rtx);
 	    }
@@ -1031,7 +1091,7 @@ gen_compare (code, x, y, need_compare)
 		  code = NE;
 		  break;
 		default:
-		  abort();
+		  abort ();
 		}
 	      
 	      return gen_rtx (code, mode, cc_reg, const0_rtx);
@@ -1083,7 +1143,6 @@ gen_compare (code, x, y, need_compare)
 	}
     }
   else
-    if (! TARGET_OLD_COMPARE)
     {
       /* reg/reg equal comparison */
       if (compare_code == EQ
@@ -1280,13 +1339,12 @@ gen_split_move_double (operands)
 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.  */
 
 int
-function_arg_partial_nregs (cum, int_mode, type, named)
+function_arg_partial_nregs (cum, mode, type, named)
      CUMULATIVE_ARGS *cum;
-     int int_mode;
+     enum machine_mode mode;
      tree type;
      int named ATTRIBUTE_UNUSED;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
   int ret;
   int size = (((mode == BLKmode && type)
 	       ? int_size_in_bytes (type)
@@ -1310,14 +1368,13 @@ function_arg_partial_nregs (cum, int_mode, type, named)
    and mode MODE, and we rely on this fact.  */
 
 void
-m32r_setup_incoming_varargs (cum, int_mode, type, pretend_size, no_rtl)
+m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
      CUMULATIVE_ARGS *cum;
-     int int_mode;
+     enum machine_mode mode;
      tree type;
      int *pretend_size;
      int no_rtl;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
   int first_anon_arg;
 
   if (no_rtl)
@@ -1353,6 +1410,7 @@ m32r_setup_incoming_varargs (cum, int_mode, type, pretend_size, no_rtl)
     }
 }
 
+
 /* Implement `va_arg'.  */
 
 rtx
@@ -1415,6 +1473,218 @@ m32r_va_arg (valist, type)
   return addr_rtx;
 }
 
+int
+m32r_adjust_cost (insn, link, dep_insn, cost)
+     rtx insn ATTRIBUTE_UNUSED;
+     rtx link ATTRIBUTE_UNUSED;
+     rtx dep_insn ATTRIBUTE_UNUSED;
+     int cost;
+{
+  return cost;
+}
+
+
+/* A C statement (sans semicolon) to update the integer scheduling
+   priority `INSN_PRIORITY(INSN)'.  Reduce the priority to execute
+   the INSN earlier, increase the priority to execute INSN later.
+   Do not define this macro if you do not need to adjust the
+   scheduling priorities of insns.
+
+   On the m32r, increase the priority of long instructions so that
+   the short instructions are scheduled ahead of the long ones.  */
+
+int
+m32r_adjust_priority (insn, priority)
+     rtx insn;
+     int priority;
+{
+  if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
+    {
+      enum rtx_code code = GET_CODE (PATTERN (insn));
+      if (code != USE && code != CLOBBER && code != ADDR_VEC
+	  && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
+	priority <<= 3;
+    }
+
+  return priority;
+}
+
+
+/* Initialize for scheduling a group of instructions.  */
+
+void
+m32r_sched_init (stream, verbose)
+     FILE * stream ATTRIBUTE_UNUSED;
+     int verbose ATTRIBUTE_UNUSED;
+{
+  m32r_sched_odd_word_p = FALSE;
+}
+
+
+/* Reorder the schedulers priority list if needed */
+
+void
+m32r_sched_reorder (stream, verbose, ready, n_ready)
+     FILE * stream;
+     int verbose;
+     rtx * ready;
+     int n_ready;
+{
+  if (TARGET_DEBUG)
+    return;
+
+  if (verbose <= 7)
+    stream = (FILE *)0;
+
+  if (stream)
+    fprintf (stream,
+	     ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
+	     n_ready,
+	     (m32r_sched_odd_word_p) ? "odd" : "even");
+
+  if (n_ready > 1)
+    {
+      rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
+      rtx * long_tail = long_head;
+      rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
+      rtx * short_tail = short_head;
+      rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
+      rtx * new_tail = new_head + (n_ready - 1);
+      int   i;
+
+      /* Loop through the instructions, classifing them as short/long.  Try
+	 to keep 2 short together and/or 1 long.  Note, the ready list is
+	 actually ordered backwards, so keep it in that manner.  */
+      for (i = n_ready-1; i >= 0; i--)
+	{
+	  rtx insn = ready[i];
+	  enum rtx_code code;
+
+	  if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
+	      || (code = GET_CODE (PATTERN (insn))) == USE
+	      || code == CLOBBER || code == ADDR_VEC)
+	    {
+	      /* Dump all current short/long insns just in case */
+	      while (long_head != long_tail)
+		*new_tail-- = *long_head++;
+
+	      while (short_head != short_tail)
+		*new_tail-- = *short_head++;
+
+	      *new_tail-- = insn;
+	      if (stream)
+		fprintf (stream,
+			 ";;\t\t::: Skipping non instruction %d\n",
+			 INSN_UID (insn));
+
+	    }
+
+	  else
+	    {
+	      if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
+		*long_tail++ = insn;
+
+	      else
+		*short_tail++ = insn;
+	    }
+	}
+
+      /* If we are on an odd word, emit a single short instruction if
+	 we can */
+      if (m32r_sched_odd_word_p && short_head != short_tail)
+	*new_tail-- = *short_head++;
+
+      /* Now dump out all of the long instructions */
+      while (long_head != long_tail)
+	*new_tail-- = *long_head++;
+
+      /* Now dump out all of the short instructions */
+      while (short_head != short_tail)
+	*new_tail-- = *short_head++;
+
+      if (new_tail+1 != new_head)
+	abort ();
+
+      bcopy ((char *) new_head, (char *) ready, sizeof (rtx) * n_ready);
+      if (stream)
+	{
+#ifdef HAIFA
+	  fprintf (stream, ";;\t\t::: New ready list:               ");
+	  debug_ready_list (ready, n_ready);
+#else
+	  int i;
+	  for (i = 0; i < n_ready; i++)
+	    {
+	      rtx insn = ready[i];
+	      enum rtx_code code;
+
+	      fprintf (stream, " %d", INSN_UID (ready[i]));
+	      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
+		  || (code = GET_CODE (PATTERN (insn))) == USE
+		  || code == CLOBBER || code == ADDR_VEC)
+		fputs ("(?)", stream);
+
+	      else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
+		fputs ("(l)", stream);
+
+	      else
+		fputs ("(s)", stream);
+	    }
+
+	  fprintf (stream, "\n");
+#endif
+	}
+    }
+}
+
+
+/* If we have a machine that can issue a variable # of instructions
+   per cycle, indicate how many more instructions can be issued
+   after the current one.  */
+int
+m32r_sched_variable_issue (stream, verbose, insn, how_many)
+     FILE * stream;
+     int verbose;
+     rtx insn;
+     int how_many;
+{
+  int orig_odd_word_p = m32r_sched_odd_word_p;
+  int short_p = FALSE;
+
+  how_many--;
+  if (how_many > 0 && !TARGET_DEBUG)
+    {
+      if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
+	how_many++;
+
+      else if (GET_CODE (PATTERN (insn)) == USE
+	       || GET_CODE (PATTERN (insn)) == CLOBBER
+	       || GET_CODE (PATTERN (insn)) == ADDR_VEC)
+	how_many++;
+
+      else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
+	{
+	  how_many = 0;
+	  m32r_sched_odd_word_p = 0;
+	}
+      else
+	{
+	  m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
+	  short_p = TRUE;
+	}
+    }
+
+  if (verbose > 7 && stream)
+    fprintf (stream,
+	     ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
+	     short_p ? "short" : "long",
+	     INSN_UID (insn),
+	     orig_odd_word_p ? "odd" : "even",
+	     how_many);
+
+  return how_many;
+}
+
 /* Cost functions.  */
 
 /* Provide the costs of an addressing mode that contains ADDR.
@@ -1638,7 +1908,7 @@ m32r_expand_prologue ()
 {
   int regno;
   int frame_size;
-  unsigned int gmask = current_frame_info.gmask;
+  unsigned int gmask;
 
   if (! current_frame_info.initialized)
     m32r_compute_frame_size (get_frame_size ());
@@ -1849,6 +2119,22 @@ m32r_output_function_epilogue (file, size)
   m32r_compute_function_type (NULL_TREE);
 }
 
+/* Return non-zero if this function is known to have a null or 1 instruction
+   epilogue.  */
+
+int
+direct_return ()
+{
+  if (!reload_completed)
+    return FALSE;
+
+  if (! current_frame_info.initialized)
+    m32r_compute_frame_size (get_frame_size ());
+
+  return current_frame_info.total_size == 0;
+}
+
+
 /* PIC */
 
 /* Emit special PIC prologues and epilogues.  */
@@ -1968,7 +2254,7 @@ m32r_print_operand (file, x, code)
 
 	if (GET_CODE (x) != CONST_DOUBLE
 	    || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
-	  abort ();
+	  fatal_insn ("Bad insn for 'A'", x);
 	REAL_VALUE_FROM_CONST_DOUBLE (d, x);
 	REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
 	fprintf (file, "%s", str);
@@ -2088,21 +2374,21 @@ m32r_print_operand (file, x, code)
       if (GET_CODE (addr) == PRE_INC)
 	{
 	  if (GET_CODE (XEXP (addr, 0)) != REG)
-	    abort ();
+	    fatal_insn ("Pre-increment address is not a register", x);
 
 	  fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
 	}
       else if (GET_CODE (addr) == PRE_DEC)
 	{
 	  if (GET_CODE (XEXP (addr, 0)) != REG)
-	    abort ();
+	    fatal_insn ("Pre-decrement address is not a register", x);
 
 	  fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
 	}
       else if (GET_CODE (addr) == POST_INC)
 	{
 	  if (GET_CODE (XEXP (addr, 0)) != REG)
-	    abort ();
+	    fatal_insn ("Post-increment address is not a register", x);
 
 	  fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
 	}
@@ -2180,7 +2466,7 @@ m32r_print_operand_address (file, addr)
 	      fputs (reg_names[REGNO (base)], file);
 	    }
 	  else
-	    abort ();
+	    fatal_insn ("Bad address", addr);
 	}
       else if (GET_CODE (base) == LO_SUM)
 	{
@@ -2196,12 +2482,12 @@ m32r_print_operand_address (file, addr)
 	  fputs (reg_names[REGNO (XEXP (base, 0))], file);
 	}
       else
-	abort ();
+	fatal_insn ("Bad address", addr);
       break;
 
     case LO_SUM :
       if (GET_CODE (XEXP (addr, 0)) != REG)
-	abort ();
+	fatal_insn ("Lo_sum not of register", addr);
       if (small_data_operand (XEXP (addr, 1), VOIDmode))
 	fputs ("sda(", file);
       else
@@ -2244,12 +2530,10 @@ zero_and_one (operand1, operand2)
 
 /* Return non-zero if the operand is suitable for use in a conditional move sequence.  */
 int
-conditional_move_operand (operand, int_mode)
+conditional_move_operand (operand, mode)
      rtx operand;
-     int int_mode;
+     enum machine_mode mode;
 {
-  enum machine_mode mode = (enum machine_mode)int_mode;
-
   /* Only defined for simple integers so far... */
   if (mode != SImode && mode != HImode && mode != QImode)
     return FALSE;
@@ -2276,13 +2560,13 @@ conditional_move_operand (operand, int_mode)
 
 /* Return true if the code is a test of the carry bit */
 int
-carry_compare_operand (op, int_mode)
+carry_compare_operand (op, mode)
      rtx op;
-     int int_mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   rtx x;
 
-  if (GET_MODE (op) != SImode && GET_MODE (op) != VOIDmode)
+  if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
     return FALSE;
 
   if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
@@ -2299,7 +2583,6 @@ carry_compare_operand (op, int_mode)
   return TRUE;
 }
 
-
 /* Generate the correct assembler code to handle the conditional loading of a
    value into a register.  It is known that the operands satisfy the
    conditional_move_operand() function above.  The destination is operand[0].
@@ -2341,6 +2624,30 @@ emit_cond_move (operands, insn)
   return buffer;
 }
 
+/* Returns true if the registers contained in the two
+   rtl expressions are different. */
+int
+m32r_not_same_reg (a, b)
+     rtx a;
+     rtx b;
+{
+  int reg_a = -1;
+  int reg_b = -2;
+  
+  while (GET_CODE (a) == SUBREG)
+    a = SUBREG_REG (a);
+  
+  if (GET_CODE (a) == REG)
+    reg_a = REGNO (a);
+  
+  while (GET_CODE (b) == SUBREG)
+    b = SUBREG_REG (b);
+  
+  if (GET_CODE (b) == REG)
+    reg_b = REGNO (b);
+  
+  return reg_a != reg_b;
+}
 
 
 /* Use a library function to move some bytes.  */
@@ -2600,7 +2907,7 @@ m32r_output_block_move (insn, operands)
 int
 m32r_block_immediate_operand (op, mode)
      rtx op;
-     int mode ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   if (GET_CODE (op) != CONST_INT
       || INTVAL (op) > MAX_MOVE_BYTES
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index 032e089..a195486 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -34,14 +34,22 @@ Boston, MA 02111-1307, USA.  */
 #undef WCHAR_TYPE_SIZE
 #undef ASM_FILE_START
 #undef ASM_OUTPUT_EXTERNAL_LIBCALL
+#undef TARGET_VERSION
+#undef CPP_SPEC
+#undef ASM_SPEC
+#undef LINK_SPEC
+#undef STARTFILE_SPEC
+#undef ENDFILE_SPEC
+#undef SUBTARGET_SWITCHES
 
 /* Print subsidiary information on the compiler version in use.  */
+#ifndef	TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (m32r)")
-
+#endif
 
 /* Switch  Recognition by gcc.c.  Add -G xx support */
 
-#undef SWITCH_TAKES_ARG
+#undef  SWITCH_TAKES_ARG
 #define SWITCH_TAKES_ARG(CHAR) \
 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
 
@@ -49,36 +57,78 @@ Boston, MA 02111-1307, USA.  */
 /* __M32R__ is defined by the existing compiler so we use that.  */
 #define CPP_PREDEFINES "-Acpu(m32r) -Amachine(m32r) -D__M32R__"
 
+/* This macro defines names of additional specifications to put in the specs
+   that can be used in various specifications like CC1_SPEC.  Its definition
+   is an initializer with a subgrouping for each command option.
 
-#define CC1_SPEC "%{G*}"
+   Each subgrouping contains a string constant, that defines the
+   specification name, and a string constant that used by the GNU CC driver
+   program.
 
-/* Options to pass on to the assembler.  */
-#undef  ASM_SPEC
-#define ASM_SPEC "%{v}"
+   Do not define this macro if it does not need to do anything.  */
 
-#if 0 /* not supported yet */
-#undef  ASM_SPEC
-#define ASM_SPEC "%{v} %{mrelax:-relax}"
+#ifndef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS
 #endif
-     
 
-#undef ASM_FINAL_SPEC
+#ifndef	ASM_CPU_SPEC
+#define	ASM_CPU_SPEC ""
+#endif
 
-#undef LINK_SPEC
+#ifndef	CPP_CPU_SPEC
+#define	CPP_CPU_SPEC ""
+#endif
+
+#ifndef	CC1_CPU_SPEC
+#define	CC1_CPU_SPEC ""
+#endif
+
+#ifndef	LINK_CPU_SPEC
+#define	LINK_CPU_SPEC ""
+#endif
+
+#ifndef STARTFILE_CPU_SPEC
+#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
+#endif
+
+#ifndef ENDFILE_CPU_SPEC
+#define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s"
+#endif
+
+#ifndef RELAX_SPEC
 #if 0 /* not supported yet */
-#define LINK_SPEC "%{v} %{mrelax:-relax}"
+#define RELAX_SPEC "%{mrelax:-relax}"
 #else
-#define LINK_SPEC "%{v}"
+#define RELAX_SPEC ""
+#endif
 #endif
 
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
+#define EXTRA_SPECS							\
+  { "asm_cpu",			ASM_CPU_SPEC },				\
+  { "cpp_cpu",			CPP_CPU_SPEC },				\
+  { "cc1_cpu",			CC1_CPU_SPEC },				\
+  { "link_cpu",			LINK_CPU_SPEC },			\
+  { "startfile_cpu",		STARTFILE_CPU_SPEC },			\
+  { "endfile_cpu",		ENDFILE_CPU_SPEC },			\
+  { "relax",			RELAX_SPEC },				\
+  SUBTARGET_EXTRA_SPECS
 
+#define CC1_SPEC "%{G*} %(cc1_cpu)"
 
-#undef ENDFILE_SPEC
-#define ENDFILE_SPEC "-lgloss crtfini.o%s"
+/* Options to pass on to the assembler.  */
+#undef  ASM_SPEC
+#define ASM_SPEC "%{v} %(asm_cpu) %(relax)"
+
+#undef  ASM_FINAL_SPEC
+
+#define LINK_SPEC "%{v} %(link_cpu) %(relax)"
+
+#undef  STARTFILE_SPEC
+#define STARTFILE_SPEC "%(startfile_cpu)"
+
+#undef  ENDFILE_SPEC
+#define ENDFILE_SPEC "%(endfile_cpu)"
 
-     
 #undef LIB_SPEC
 
 /* Run-time compilation parameters selecting different hardware subsets.  */
@@ -91,27 +141,27 @@ extern int target_flags;
    This can cause incorrect debugging information as line numbers may
    turn out wrong.  This shouldn't be specified unless accompanied with -O2
    [where the user expects debugging information to be less accurate].  */
-#define TARGET_RELAX_MASK 1
+#define TARGET_RELAX_MASK 	(1 << 0)
 
 /* For miscellaneous debugging purposes.  */
-#define TARGET_DEBUG_MASK 2
-#define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
+#define TARGET_DEBUG_MASK 	(1 << 1)
+#define TARGET_DEBUG 		(target_flags & TARGET_DEBUG_MASK)
 
 /* Align loops to 32 byte boundaries (cache line size).  */
 /* ??? This option is experimental and is not documented.  */
-#define TARGET_ALIGN_LOOPS_MASK 4
-#define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
+#define TARGET_ALIGN_LOOPS_MASK (1 << 2)
+#define TARGET_ALIGN_LOOPS 	(target_flags & TARGET_ALIGN_LOOPS_MASK)
 
-/* Use old compare/branch support (kept around for awhile for
-   comparison and backoff purposes).  */
-/* ??? This option is experimental and is not documented.
-   Eventually it will be deleted.  */
-#define TARGET_OLD_COMPARE_MASK 8
-#define TARGET_OLD_COMPARE (target_flags & TARGET_OLD_COMPARE_MASK)
+/* Change issue rate.  */
+#define TARGET_ISSUE_RATE_MASK	(1 << 3)
+#define TARGET_ISSUE_RATE	(target_flags & TARGET_ISSUE_RATE_MASK)
 
-/* Target machine to compile for.  */
-#define TARGET_M32R 1
+/* Change branch cost */
+#define TARGET_BRANCH_COST_MASK	(1 << 4)
+#define TARGET_BRANCH_COST	(target_flags & TARGET_BRANCH_COST_MASK)
 
+/* Target machine to compile for.  */
+#define TARGET_M32R 		1
 
 /* Macro to define tables used to set the flags.
    This is a list in braces of pairs in braces,
@@ -119,48 +169,45 @@ extern int target_flags;
    where VALUE is the bits to set or minus the bits to clear.
    An empty string NAME is used to identify the default VALUE.  */
 
-#define TARGET_SWITCHES \
-{ \
-/*  { "relax",			TARGET_RELAX_MASK },			\
-    { "no-relax",		-TARGET_RELAX_MASK },*/			\
-    { "debug",			TARGET_DEBUG_MASK },			\
-    { "align-loops",		TARGET_ALIGN_LOOPS_MASK },		\
-    { "no-align-loops",		-TARGET_ALIGN_LOOPS_MASK },		\
-    { "old-compare",		TARGET_OLD_COMPARE_MASK },		\
-    { "no-old-compare",		-TARGET_OLD_COMPARE_MASK },		\
-    SUBTARGET_SWITCHES							\
-    { "", TARGET_DEFAULT }						\
-}
-
-#define TARGET_DEFAULT (0)
-
+#ifndef SUBTARGET_SWITCHES
 #define SUBTARGET_SWITCHES
+#endif
 
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
-   command options that have values.  Its definition is an
-   initializer with a subgrouping for each command option.
-
-   Each subgrouping contains a string constant, that defines the
-   fixed part of the option name, and the address of a variable. 
-   The variable, type `char *', is set to the variable part of the
-   given option if the fixed part matches.  The actual option name
-   is made by appending `-m' to the specified name.
-
-   Here is an example which defines `-mshort-data-NUMBER'.  If the
-   given option is `-mshort-data-512', the variable `m88k_short_data'
-   will be set to the string `"512"'.
+#ifndef TARGET_DEFAULT
+#define TARGET_DEFAULT 0
+#endif
 
-	extern char *m88k_short_data;
-	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
+#define TARGET_SWITCHES							\
+{									\
+/*  { "relax",			TARGET_RELAX_MASK, "" },		\
+    { "no-relax",		-TARGET_RELAX_MASK, "" },*/		\
+    { "debug",			TARGET_DEBUG_MASK, 			\
+	"Display compile time statistics" },				\
+    { "align-loops",		TARGET_ALIGN_LOOPS_MASK, 		\
+	"Align all loops to 32 byte boundary" },			\
+    { "no-align-loops",		-TARGET_ALIGN_LOOPS_MASK, "" },		\
+    { "issue-rate=1",		TARGET_ISSUE_RATE_MASK, 		\
+	"Only issue one instruction per cycle" },			\
+    { "issue-rate=2",		-TARGET_ISSUE_RATE_MASK, "" },		\
+    { "branch-cost=1",		TARGET_BRANCH_COST_MASK, 		\
+	"Prefer branches over conditional execution" },			\
+    { "branch-cost=2",		-TARGET_BRANCH_COST_MASK, "" },		\
+    SUBTARGET_SWITCHES							\
+    { "", TARGET_DEFAULT, "" }						\
+}
 
-extern char *m32r_model_string;
-extern char *m32r_sdata_string;
+extern const char * m32r_model_string;
+extern const char * m32r_sdata_string;
 
+#ifndef SUBTARGET_OPTIONS
+#define SUBTARGET_OPTIONS
+#endif
 
-#define TARGET_OPTIONS \
-{						\
-  { "model=",	&m32r_model_string	},	\
-  { "sdata=",	&m32r_sdata_string	},	\
+#define TARGET_OPTIONS							\
+{									\
+  { "model=", & m32r_model_string, "Code size: small, medium or large" },\
+  { "sdata=", & m32r_sdata_string, "Small data area: none, sdata, use" } \
+  SUBTARGET_OPTIONS							\
 }
 
 /* Code Models
@@ -196,7 +243,9 @@ extern enum m32r_model m32r_model;
 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
 
 /* The default is the small model.  */
+#ifndef M32R_MODEL_DEFAULT
 #define M32R_MODEL_DEFAULT "small"
+#endif
 
 /* Small Data Area
 
@@ -232,7 +281,9 @@ extern enum m32r_model m32r_model;
 
 /* Maximum size of variables that go in .sdata/.sbss.
    The -msdata=foo switch also controls how small variables are handled.  */
+#ifndef SDATA_DEFAULT_SIZE
 #define SDATA_DEFAULT_SIZE 8
+#endif
 
 extern int g_switch_value;		/* value of the -G xx switch */
 extern int g_switch_set;		/* whether -G xx was passed.  */
@@ -246,13 +297,21 @@ extern enum m32r_sdata m32r_sdata;
 
 /* Default is to disable the SDA
    [for upward compatibility with previous toolchains].  */
+#ifndef M32R_SDATA_DEFAULT
 #define M32R_SDATA_DEFAULT "none"
+#endif
 
 /* Define this macro as a C expression for the initializer of an array of
    strings to tell the driver program which options are defaults for this
    target and thus do not need to be handled specially when using
    `MULTILIB_OPTIONS'.  */
-#define MULTILIB_DEFAULTS { "mmodel=small", "m32r" }
+#ifndef SUBTARGET_MULTILIB_DEFAULTS
+#define SUBTARGET_MULTILIB_DEFAULTS
+#endif
+
+#ifndef MULTILIB_DEFAULTS
+#define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS }
+#endif
 
 /* Sometimes certain combinations of command options do not make
    sense on a particular target machine.  You can define a macro
@@ -263,11 +322,39 @@ extern enum m32r_sdata m32r_sdata;
    Don't use this macro to turn on various extra optimizations for
    `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
 
-#define OVERRIDE_OPTIONS \
-do {				\
-  /* These need to be done at start up.  It's convenient to do them here.  */ \
-  m32r_init ();			\
-} while (0)
+#ifndef SUBTARGET_OVERRIDE_OPTIONS
+#define SUBTARGET_OVERRIDE_OPTIONS
+#endif
+
+#define OVERRIDE_OPTIONS			\
+  do						\
+    {						\
+      /* These need to be done at start up.	\
+	 It's convenient to do them here.  */	\
+      m32r_init ();				\
+      SUBTARGET_OVERRIDE_OPTIONS		\
+    }						\
+  while (0)
+
+#ifndef SUBTARGET_OPTIMIZATION_OPTIONS
+#define SUBTARGET_OPTIMIZATION_OPTIONS
+#endif
+
+#define OPTIMIZATION_OPTIONS(LEVEL, SIZE)	\
+  do						\
+    {						\
+      if (LEVEL == 1)				\
+	flag_regmove = TRUE;			\
+      						\
+      if (SIZE)					\
+	{					\
+	  flag_omit_frame_pointer = TRUE;	\
+	  flag_strength_reduce = FALSE;		\
+	}					\
+      						\
+      SUBTARGET_OPTIMIZATION_OPTIONS		\
+    }						\
+  while (0)
 
 /* Define this macro if debugging can be performed even without a
    frame pointer.  If this macro is defined, GNU CC will turn on the
@@ -314,12 +401,12 @@ do {				\
    the value is constrained to be within the bounds of the declared
    type, but kept valid in the wider mode.  The signedness of the
    extension may differ from that of the type.  */
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
-if (GET_MODE_CLASS (MODE) == MODE_INT		\
-    && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)	\
-{						\
-  (MODE) = SImode;				\
-}
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
+  if (GET_MODE_CLASS (MODE) == MODE_INT		\
+      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)	\
+    {						\
+      (MODE) = SImode;				\
+    }
 
 /* Define this macro if the promotion described by `PROMOTE_MODE'
    should also be done for outgoing function arguments.  */
@@ -362,15 +449,15 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
 #define FASTEST_ALIGNMENT 32
 
 /* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)	\
   ((TREE_CODE (EXP) == STRING_CST	\
     && (ALIGN) < FASTEST_ALIGNMENT)	\
    ? FASTEST_ALIGNMENT : (ALIGN))
 
 /* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
+#define DATA_ALIGNMENT(TYPE, ALIGN)					\
+  (TREE_CODE (TYPE) == ARRAY_TYPE					\
+   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode				\
    && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
 
 /* Set this nonzero if move instructions will actually fail to work
@@ -411,7 +498,14 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
    from 0 to just below FIRST_PSEUDO_REGISTER.
    All registers that the compiler knows about must be given numbers,
    even those that are not normally considered general registers.  */
-#define FIRST_PSEUDO_REGISTER 18
+
+#define M32R_NUM_REGISTERS 	19
+
+#ifndef SUBTARGET_NUM_REGISTERS
+#define SUBTARGET_NUM_REGISTERS 0
+#endif
+
+#define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS)
 	
 /* 1 for registers that have pervasive standard uses
    and are not available for the register allocator.
@@ -427,15 +521,21 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
    15    - stack pointer
    16    - arg pointer
    17    - carry flag
+   18	 - accumulator
 
-   
    By default, the extension registers are not available.  */
 
-#define FIXED_REGISTERS \
-{ 0, 0, 0, 0, 0, 0, 0, 0,	\
-  0, 0, 0, 0, 0, 0, 0, 1,	\
-  1, 1 }
+#ifndef SUBTARGET_FIXED_REGISTERS
+#define SUBTARGET_FIXED_REGISTERS
+#endif
 
+#define FIXED_REGISTERS		\
+{				\
+  0, 0, 0, 0, 0, 0, 0, 0,	\
+  0, 0, 0, 0, 0, 0, 0, 1,	\
+  1, 1, 1			\
+  SUBTARGET_FIXED_REGISTERS	\
+}
 
 /* 1 for registers not available across function calls.
    These must include the FIXED_REGISTERS and also any
@@ -444,11 +544,17 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
    and the register where structure-value addresses are passed.
    Aside from that, you can include as many other registers as you like.  */
 
-#define CALL_USED_REGISTERS \
-{ 1, 1, 1, 1, 1, 1, 1, 1,	\
-  0, 0, 0, 0, 0, 0, 1, 1,	\
-  1, 1 }
+#ifndef SUBTARGET_CALL_USED_REGISTERS
+#define SUBTARGET_CALL_USED_REGISTERS
+#endif
 
+#define CALL_USED_REGISTERS	\
+{				\
+  1, 1, 1, 1, 1, 1, 1, 1,	\
+  0, 0, 0, 0, 0, 0, 1, 1,	\
+  1, 1, 1			\
+  SUBTARGET_CALL_USED_REGISTERS	\
+}
 
 /* Zero or more C statements that may conditionally modify two variables
    `fixed_regs' and `call_used_regs' (both of type `char []') after they
@@ -459,17 +565,33 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
 
    You need not define this macro if it has no work to do.  */
 
-/*#define CONDITIONAL_REGISTER_USAGE*/
+#ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE
+#define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE
+#endif
 
 /* If defined, an initializer for a vector of integers, containing the
    numbers of hard registers in the order in which GNU CC should
    prefer to use them (from most preferred to least).  */
+
+#ifndef SUBTARGET_REG_ALLOC_ORDER
+#define SUBTARGET_REG_ALLOC_ORDER
+#endif
+
 #if 1 /* better for int code */
-#define REG_ALLOC_ORDER \
-{ 4, 5, 6, 7, 2, 3, 8, 9, 10, 11, 12, 13, 14, 0, 1, 15, 16, 17 }
+#define REG_ALLOC_ORDER				\
+{						\
+  4,  5,  6,  7,  2,  3,  8,  9, 10,		\
+  11, 12, 13, 14,  0,  1, 15, 16, 17, 18	\
+  SUBTARGET_REG_ALLOC_ORDER			\
+}
+
 #else /* better for fp code at expense of int code */
-#define REG_ALLOC_ORDER \
-{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 }
+#define REG_ALLOC_ORDER				\
+{						\
+   0,  1,  2,  3,  4,  5,  6,  7,  8,		\
+   9, 10, 11, 12, 13, 14, 15, 16, 17, 18	\
+  SUBTARGET_REG_ALLOC_ORDER			\
+}
 #endif
 
 /* Return number of consecutive hard regs needed starting at reg REGNO
@@ -525,38 +647,61 @@ extern unsigned int m32r_mode_class[];
    It is important that any condition codes have class NO_REGS.
    See `register_operand'.  */
 
-enum reg_class {
-  NO_REGS, CARRY_REG, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
+enum reg_class
+{
+  NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
 };
 
-#define N_REG_CLASSES (int) LIM_REG_CLASSES
+#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
 
 /* Give names of register classes as strings for dump file.   */
 #define REG_CLASS_NAMES \
-{ "NO_REGS", "CARRY_REG", "GENERAL_REGS", "ALL_REGS" }
+  { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" }
 
 /* Define which registers fit in which classes.
    This is an initializer for a vector of HARD_REG_SET
    of length N_REG_CLASSES.  */
 
-#define REG_CLASS_CONTENTS \
-{ {0}, {0x20000}, {0x1ffff}, {0x3ffff} }
+#ifndef SUBTARGET_REG_CLASS_CARRY
+#define SUBTARGET_REG_CLASS_CARRY 0
+#endif
+
+#ifndef SUBTARGET_REG_CLASS_ACCUM
+#define SUBTARGET_REG_CLASS_ACCUM 0
+#endif
+
+#ifndef SUBTARGET_REG_CLASS_GENERAL
+#define SUBTARGET_REG_CLASS_GENERAL 0
+#endif
+
+#ifndef SUBTARGET_REG_CLASS_ALL
+#define SUBTARGET_REG_CLASS_ALL 0
+#endif
 
+#define REG_CLASS_CONTENTS						\
+{									\
+  { 0x00000 },								\
+  { 0x20000 | SUBTARGET_REG_CLASS_CARRY },				\
+  { 0x40000 | SUBTARGET_REG_CLASS_ACCUM },				\
+  { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL },				\
+  { 0x7ffff | SUBTARGET_REG_CLASS_ALL },				\
+}
 
 /* The same information, inverted:
    Return the class number of the smallest class containing
    reg number REGNO.  This could be a conditional expression
    or could index an array.  */
 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
-#define REGNO_REG_CLASS(REGNO) \
-(m32r_regno_reg_class[REGNO])
+#define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO])
 
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS GENERAL_REGS
 #define BASE_REG_CLASS GENERAL_REGS
 
-/* Get reg_class from a letter such as appears in the machine description.  */
-#define REG_CLASS_FROM_LETTER(C) NO_REGS
+#define REG_CLASS_FROM_LETTER(C)					\
+((C) == 'c'	? CARRY_REG						\
+ : (C) == 'a'	? ACCUM_REGS						\
+ :		  NO_REGS)
 
 /* These assume that REGNO is a hard or pseudo reg number.
    They give nonzero only if REGNO is a hard reg of the suitable class
@@ -596,15 +741,20 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
    'P' is used for 16 bit signed immediates for compares
        (values in the range -32767 to +32768).  */
 
-/* local to this file */
+/* Return true if a value is inside a range.  */
+#define IN_RANGE_P(VALUE, LOW, HIGH)					\
+  (((unsigned HOST_WIDE_INT)((VALUE) - (LOW)))				\
+   <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW))))
+
+/* Local to this file.  */
 #define INT8_P(X) ((X) >= -0x80 && (X) <= 0x7f)
 #define INT16_P(X) ((X) >= -0x8000 && (X) <= 0x7fff)
 #define CMP_INT16_P(X) ((X) >= -0x7fff && (X) <= 0x8000)
-#define UINT16_P(X) ((X) >= 0 && (X) <= 0xffff)
+#define UINT16_P(X) (((unsigned HOST_WIDE_INT)(X)) <= 0xffff)
 #define UPPER16_P(X) (((X) & 0xffff) == 0				\
 		      && ((X) >> 16) >= -0x8000				\
 		      && ((X) >> 16) <= 0x7fff)
-#define UINT24_P(X) ((X) >= 0 && (X) < 0x1000000)
+#define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) < 0x1000000)
 #define INT32_P(X) (((X) >= -(HOST_WIDE_INT) 0x80000000			\
 		     && (X) <= (HOST_WIDE_INT) 0x7fffffff)		\
 		    || (unsigned HOST_WIDE_INT) (X) <= 0xffffffff)
@@ -639,25 +789,23 @@ extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
    be 0 regardless of VALUE.  */
 /* Q is for symbolic addresses loadable with ld24.
    R is for symbolic addresses when ld24 can't be used.
-   S is unused.
+   S is for stores with pre {inc,dec}rement
    T is for indirect of a pointer.
-   U is for pushes and pops of the stack pointer.  */
+   U is for loads with post increment.  */
 
 #define EXTRA_CONSTRAINT(VALUE, C)					\
-((C) == 'Q'								\
- ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF)			\
-    || addr24_operand (VALUE, VOIDmode))				\
- : (C) == 'R'								\
- ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF)			\
-    || addr32_operand (VALUE, VOIDmode))				\
- : (C) == 'S'								\
- ? 0									\
- : (C) == 'T'								\
- ?  (GET_CODE (VALUE) == MEM						\
-     && memreg_operand (VALUE, GET_MODE (VALUE)))			\
- : (C) == 'U'								\
- ?  (GET_CODE (VALUE) == MEM						\
-     && PUSH_POP_P (GET_MODE (VALUE), XEXP (VALUE, 0)))			\
+(  (C) == 'Q' ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF)	\
+		 || addr24_operand (VALUE, VOIDmode))			\
+ : (C) == 'R' ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF)	\
+		 || addr32_operand (VALUE, VOIDmode))			\
+ : (C) == 'S' ? (GET_CODE (VALUE) == MEM				\
+		 && STORE_PREINC_PREDEC_P (GET_MODE (VALUE),		\
+					   XEXP (VALUE, 0)))		\
+ : (C) == 'T' ? (GET_CODE (VALUE) == MEM				\
+		 && memreg_operand (VALUE, GET_MODE (VALUE)))		\
+ : (C) == 'U' ? (GET_CODE (VALUE) == MEM				\
+		 && LOAD_POSTINC_P (GET_MODE (VALUE),			\
+				    XEXP (VALUE, 0)))			\
  : 0)
 
 /* Stack layout and stack pointer usage.  */
@@ -745,18 +893,31 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
 #define RETURN_ADDR_REGNUM 14
 /* #define GP_REGNUM 12 */
 #define CARRY_REGNUM 17
+#define ACCUM_REGNUM 18
 #define M32R_MAX_INT_REGS 16
 
-     
-#define GPR_P(REGNO) ((unsigned) (REGNO) < M32R_MAX_INT_REGS)
+#ifndef SUBTARGET_GPR_P
+#define SUBTARGET_GPR_P(REGNO) 0
+#endif
+
+#ifndef SUBTARGET_ACCUM_P
+#define SUBTARGET_ACCUM_P(REGNO) 0
+#endif
+
+#ifndef SUBTARGET_CARRY_P
+#define SUBTARGET_CARRY_P(REGNO) 0
+#endif
+
+#define GPR_P(REGNO)   (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO))
+#define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO))
+#define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO))
 
 /* Eliminating the frame and arg pointers.  */
 
 /* A C expression which is nonzero if a function must have and use a
    frame pointer.  This expression is evaluated in the reload pass.
    If its value is nonzero the function will have a frame pointer.  */
-#define FRAME_POINTER_REQUIRED \
-(current_function_calls_alloca)
+#define FRAME_POINTER_REQUIRED current_function_calls_alloca
 
 #if 0
 /* C statement to store the difference between the frame pointer
@@ -776,10 +937,10 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
    Note that the elimination of the argument pointer with the stack
    pointer is specified first since that is the preferred elimination.  */
 
-#define ELIMINABLE_REGS \
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },			\
- { ARG_POINTER_REGNUM,	 STACK_POINTER_REGNUM },			\
- { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM }}			\
+#define ELIMINABLE_REGS					\
+{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },	\
+ { ARG_POINTER_REGNUM,	 STACK_POINTER_REGNUM },	\
+ { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM }}
 
 /* A C expression that returns non-zero if the compiler is allowed to
    try to replace register number FROM-REG with register number
@@ -788,10 +949,10 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
    cases preventing register elimination are things that the compiler
    already knows about.  */
 
-#define CAN_ELIMINATE(FROM, TO) \
-((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM		\
- ? ! frame_pointer_needed						\
- : 1)
+#define CAN_ELIMINATE(FROM, TO)						\
+  ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM		\
+   ? ! frame_pointer_needed						\
+   : 1)
 
 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
    specifies the initial difference between the specified pair of
@@ -837,7 +998,7 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
    which.  */
 #if 0
 #define REG_PARM_STACK_SPACE(FNDECL) \
-(M32R_MAX_PARM_REGS * UNITS_PER_WORD)
+  (M32R_MAX_PARM_REGS * UNITS_PER_WORD)
 #endif
 
 /* Value is the number of bytes of arguments automatically
@@ -849,7 +1010,7 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
 
 /* Nonzero if we do not know how to pass TYPE solely in registers. */
-#define MUST_PASS_IN_STACK(MODE,TYPE)			\
+#define MUST_PASS_IN_STACK(MODE, TYPE)			\
   ((TYPE) != 0						\
    && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST	\
        || TREE_ADDRESSABLE (TYPE)))
@@ -864,26 +1025,26 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
    for a call to a function whose data type is FNTYPE.
    For a library call, FNTYPE is 0.  */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
-((CUM) = 0)
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
+  ((CUM) = 0)
 
 /* The number of registers used for parameter passing.  Local to this file.  */
 #define M32R_MAX_PARM_REGS 4
 
 /* 1 if N is a possible register number for function argument passing.  */
 #define FUNCTION_ARG_REGNO_P(N) \
-((unsigned) (N) < M32R_MAX_PARM_REGS)
+  ((unsigned) (N) < M32R_MAX_PARM_REGS)
 
 /* The ROUND_ADVANCE* macros are local to this file.  */
 /* Round SIZE up to a word boundary.  */
 #define ROUND_ADVANCE(SIZE) \
-(((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+  (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 
 /* Round arg MODE/TYPE up to the next word boundary.  */
 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
-((MODE) == BLKmode				\
- ? ROUND_ADVANCE (int_size_in_bytes (TYPE))	\
- : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
+  ((MODE) == BLKmode				\
+   ? ROUND_ADVANCE (int_size_in_bytes (TYPE))	\
+   : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
 
 /* Round CUM up to the necessary point for argument MODE/TYPE.  */
 #if 0
@@ -902,7 +1063,7 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
    we're given).
    This macro is only used in this file.  */
 #define PASS_IN_REG_P(CUM, MODE, TYPE, NAMED) \
-(ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
+  (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
 
 /* Determine where to put an argument to a function.
    Value is zero to push the argument on the stack,
@@ -919,16 +1080,16 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
    and the rest are pushed.  */
 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-(PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))				\
- ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
- : 0)
+  (PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))			\
+   ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
+   : 0)
 
 /* ??? Quick hack to try to get varargs working the normal way.  */
 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
-(((! current_function_varargs || (NAMED))				\
-  && PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED)))			\
- ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
- : 0)
+  (((! current_function_varargs || (NAMED))				\
+    && PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED)))			\
+   ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
+   : 0)
 
 /* A C expression for the number of words, at the beginning of an
    argument, must be put in registers.  The value must be zero for
@@ -953,13 +1114,13 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
    appropriate for passing a pointer to that type.  */
 /* All arguments greater than 8 bytes are passed this way.  */
 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
-((TYPE) && int_size_in_bytes (TYPE) > 8)
+  ((TYPE) && int_size_in_bytes (TYPE) > 8)
 
 /* Update the data in CUM to advance over an argument
    of mode MODE and data type TYPE.
    (TYPE is null for libcalls where that information may not be available.)  */
 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
-((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
+  ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
 	  + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
 
 /* If defined, a C expression that gives the alignment boundary, in bits,
@@ -1001,7 +1162,7 @@ M32R_STACK_ALIGN (current_function_outgoing_args_size)
    this case.  */
 
 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
-m32r_setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
+ m32r_setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
 
 /* Implement `va_arg'.  */
 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
@@ -1118,11 +1279,9 @@ do { \
 
 /* We have post-inc load and pre-dec,pre-inc store,
    but only for 4 byte vals.  */
-#if 0
 #define HAVE_PRE_DECREMENT 1
 #define HAVE_PRE_INCREMENT 1
 #define HAVE_POST_INCREMENT 1
-#endif
 
 /* Recognize any constant value that is a valid address.  */
 #define CONSTANT_ADDRESS_P(X) \
@@ -1135,11 +1294,11 @@ do { \
    We allow all CONST_DOUBLE's as the md file patterns will force the
    constant to memory if they can't handle them.  */
 
-#define LEGITIMATE_CONSTANT_P(X) \
-(! (GET_CODE (X) == CONST \
-    && GET_CODE (XEXP (X, 0)) == PLUS \
-    && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
-    && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
+#define LEGITIMATE_CONSTANT_P(X)					\
+(! (GET_CODE (X) == CONST						\
+    && GET_CODE (XEXP (X, 0)) == PLUS					\
+    && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF			\
+    && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT			\
     && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
 
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
@@ -1166,7 +1325,7 @@ do { \
 
 /* Nonzero if X is a hard reg that can be used as a base reg
    or if it is a pseudo reg.  */
-#define REG_OK_FOR_BASE_P(X) \
+#define REG_OK_FOR_BASE_P(X)		\
 (GPR_P (REGNO (X))			\
  || (REGNO (X)) == ARG_POINTER_REGNUM	\
  || REGNO (X) >= FIRST_PSEUDO_REGISTER)
@@ -1181,21 +1340,20 @@ do { \
    The MODE argument is the machine mode for the MEM expression
    that wants to use this address.  */
 
-/* local to this file */
-#define RTX_OK_FOR_BASE_P(X) \
-(REG_P (X) && REG_OK_FOR_BASE_P (X))
+/* Local to this file.  */
+#define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
 
-/* local to this file */
+/* Local to this file.  */
 #define RTX_OK_FOR_OFFSET_P(X) \
 (GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
 
-/* local to this file */
+/* Local to this file.  */
 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X)				\
 (GET_CODE (X) == PLUS							\
  && RTX_OK_FOR_BASE_P (XEXP (X, 0))					\
  && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
 
-/* local to this file */
+/* Local to this file.  */
 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
    since more than one instruction will be required.  */
 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X)				\
@@ -1204,13 +1362,21 @@ do { \
  && RTX_OK_FOR_BASE_P (XEXP (X, 0))					\
  && CONSTANT_P (XEXP (X, 1)))
 
-/* local to this file */
-/* Memory address that is a push/pop of the stack pointer.  */
-#define PUSH_POP_P(MODE, X)						\
-((MODE) == SImode							\
- && (GET_CODE (X) == POST_INC						\
-     || GET_CODE (X) == PRE_INC						\
-     || GET_CODE (X) == PRE_DEC))
+/* Local to this file.  */
+/* Is this a load and increment operation.  */
+#define LOAD_POSTINC_P(MODE, X)						\
+(((MODE) == SImode || (MODE) == SFmode)					\
+ && GET_CODE (X) == POST_INC						\
+ && GET_CODE (XEXP (X, 0)) == REG					\
+ && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
+
+/* Local to this file.  */
+/* Is this a increment/decrement and store operation.  */
+#define STORE_PREINC_PREDEC_P(MODE, X)					\
+(((MODE) == SImode || (MODE) == SFmode)					\
+ && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC)		\
+ && GET_CODE (XEXP (X, 0)) == REG					\
+ && RTX_OK_FOR_BASE_P (XEXP (X, 0)))
 
 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
 { if (RTX_OK_FOR_BASE_P (X))						\
@@ -1219,7 +1385,9 @@ do { \
     goto ADDR;								\
   if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X)))			\
     goto ADDR;								\
-  if (PUSH_POP_P ((MODE), (X)))						\
+  if (LOAD_POSTINC_P ((MODE), (X)))					\
+    goto ADDR;								\
+  if (STORE_PREINC_PREDEC_P ((MODE), (X)))				\
     goto ADDR;								\
 }
 
@@ -1277,7 +1445,7 @@ do {									\
    return it with a return statement.  Otherwise, break from the switch.  */
 /* Small integers are as cheap as registers.  4 byte values can be fetched
    as immediate constants - let's give that the cost of an extra insn.  */
-#define CONST_COSTS(X, CODE, OUTER_CODE) \
+#define CONST_COSTS(X, CODE, OUTER_CODE)			\
   case CONST_INT :						\
     if (INT16_P (INTVAL (X)))					\
       return 0;							\
@@ -1311,7 +1479,7 @@ do {									\
 /* A value of 2 here causes GCC to avoid using branches in comparisons like
    while (a < N && a).  Branches aren't that expensive on the M32R so
    we define this as 1.  Defining it as 2 had a heavy hit in fp-bit.c.  */
-#define BRANCH_COST 1
+#define BRANCH_COST ((TARGET_BRANCH_COST) ? 2 : 1)
 
 /* Provide the costs of a rtl expression.  This is in the body of a
    switch on CODE.  The purpose for the cost of MULT is to encourage
@@ -1319,14 +1487,14 @@ do {									\
 
    If we need more than 12 insns to do a multiply, then go out-of-line,
    since the call overhead will be < 10% of the cost of the multiply.  */
-#define RTX_COSTS(X, CODE, OUTER_CODE) \
-  case MULT :						\
-    return COSTS_N_INSNS (3);				\
-  case DIV :						\
-  case UDIV :						\
-  case MOD :						\
-  case UMOD :						\
-    return COSTS_N_INSNS (10);				\
+#define RTX_COSTS(X, CODE, OUTER_CODE)	\
+  case MULT :				\
+    return COSTS_N_INSNS (3);		\
+  case DIV :				\
+  case UDIV :				\
+  case MOD :				\
+  case UMOD :				\
+    return COSTS_N_INSNS (10);
 
 /* Nonzero if access to memory by bytes is slow and undesirable.
    For RISC chips, it means that access to memory by bytes is no
@@ -1343,28 +1511,22 @@ do {									\
    register.  */
 #define NO_RECURSIVE_FUNCTION_CSE
 
-/* Enable the register move pass.
-   This is useful for machines with only 2 address instructions.
-   It's not currently enabled by default because on the stanford benchmarks
-   the improvement wasn't significant and in a couple of cases caused a
-   significant de-optimization.  */
-/* #define ENABLE_REGMOVE_PASS */
-
 /* A C statement (sans semicolon) to update the integer variable COST based on
    the relationship between INSN that is dependent on DEP_INSN through the
    dependence LINK.  The default is to make no adjustment to COST.  This can be
    used for example to specify to the scheduler that an output- or
    anti-dependence does not incur the same cost as a data-dependence.  */
 
-/* #define ADJUST_COST(INSN,LINK,DEP_INSN,COST)				\
-  (COST) = m32r_adjust_cost (INSN, LINK, DEP_INSN, COST) */
+#define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
+  (COST) = m32r_adjust_cost (INSN, LINK, DEP_INSN, COST)
 
 /* A C statement (sans semicolon) to update the integer scheduling
    priority `INSN_PRIORITY(INSN)'.  Reduce the priority to execute
    the INSN earlier, increase the priority to execute INSN later.
    Do not define this macro if you do not need to adjust the
    scheduling priorities of insns.  */
-/* #define ADJUST_PRIORITY (INSN) */
+#define ADJUST_PRIORITY(INSN) \
+  INSN_PRIORITY (INSN) = m32r_adjust_priority (INSN, INSN_PRIORITY (INSN))
 
 /* Macro to determine whether the Haifa scheduler is used.  */
 #ifdef HAIFA
@@ -1374,10 +1536,32 @@ do {									\
 #endif
 
 /* Indicate how many instructions can be issued at the same time.
-   This is 1/2 of a lie.  The m32r can issue only 1 long insn at
-   once, but 2.  However doing so allows the scheduler to group
-   the two short insns together.  */
-#define ISSUE_RATE 2
+   This is sort of a lie.  The m32r can issue only 1 long insn at
+   once, but it can issue 2 short insns.  The default therefore is
+   set at 2, but this can be overridden by the command line option
+   -missue-rate=1 */
+#define ISSUE_RATE ((TARGET_ISSUE_RATE) ? 1 : 2)
+
+/* If we have a machine that can issue a variable # of instructions
+   per cycle, indicate how many more instructions can be issued
+   after the current one.  */
+#define MD_SCHED_VARIABLE_ISSUE(STREAM, VERBOSE, INSN, HOW_MANY)	\
+(HOW_MANY) = m32r_sched_variable_issue (STREAM, VERBOSE, INSN, HOW_MANY)
+
+/* Whether we are on an odd word boundary while scheduling.  */
+extern int m32r_sched_odd_word_p;
+
+/* Hook to run before scheduling a block of insns.  */
+#define MD_SCHED_INIT(STREAM, VERBOSE) m32r_sched_init (STREAM, VERBOSE)
+
+/* Hook to reorder the list of ready instructions.  */
+#define MD_SCHED_REORDER(STREAM, VERBOSE, READY, N_READY, CLOCK, CIM) 	\
+  do									\
+    {									\
+      m32r_sched_reorder (STREAM, VERBOSE, READY, N_READY);		\
+      CIM = issue_rate;							\
+    }									\
+  while (0)
 
 /* When the `length' insn attribute is used, this macro specifies the
    value to be assigned to the address of the first insn in a
@@ -1394,26 +1578,26 @@ do {									\
 #define SDATA_SECTION_ASM_OP	"\t.section .sdata"
 #define SBSS_SECTION_ASM_OP	"\t.section .sbss"
 /* This one is for svr4.h.  */
-#undef CONST_SECTION_ASM_OP
+#undef  CONST_SECTION_ASM_OP
 #define CONST_SECTION_ASM_OP	"\t.section .rodata"
 
 /* A list of names for sections other than the standard two, which are
    `in_text' and `in_data'.  You need not define this macro
    on a system with no other sections (that GCC needs to use).  */
-#undef EXTRA_SECTIONS
+#undef  EXTRA_SECTIONS
 #define EXTRA_SECTIONS in_sdata, in_sbss, in_const, in_ctors, in_dtors
 
 /* One or more functions to be defined in "varasm.c".  These
    functions should do jobs analogous to those of `text_section' and
    `data_section', for your additional sections.  Do not define this
    macro if you do not define `EXTRA_SECTIONS'.  */
-#undef EXTRA_SECTION_FUNCTIONS
-#define EXTRA_SECTION_FUNCTIONS \
-CONST_SECTION_FUNCTION \
-CTORS_SECTION_FUNCTION \
-DTORS_SECTION_FUNCTION \
-SDATA_SECTION_FUNCTION \
-SBSS_SECTION_FUNCTION
+#undef  EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS	\
+  CONST_SECTION_FUNCTION	\
+  CTORS_SECTION_FUNCTION	\
+  DTORS_SECTION_FUNCTION	\
+  SDATA_SECTION_FUNCTION	\
+  SBSS_SECTION_FUNCTION
 
 #define SDATA_SECTION_FUNCTION						\
 void									\
@@ -1441,8 +1625,7 @@ sbss_section ()								\
    output of EXP.  You can assume that EXP is either a `VAR_DECL' node
    or a constant of some sort.  RELOC indicates whether the initial value
    of EXP requires link-time relocations.  */
-extern void m32r_select_section ();
-#undef SELECT_SECTION
+#undef  SELECT_SECTION
 #define SELECT_SECTION(EXP, RELOC) m32r_select_section ((EXP), (RELOC))
 
 /* A C statement or statements to switch to the appropriate section for
@@ -1573,54 +1756,64 @@ do {							\
 #define ASM_APP_OFF ""
 
 /* This is how to output an assembler line defining a `char' constant.  */
-#define ASM_OUTPUT_CHAR(FILE, VALUE) \
-do {						\
-  fprintf (FILE, "\t.byte\t");			\
-  output_addr_const (FILE, (VALUE));		\
-  fprintf (FILE, "\n");				\
-} while (0)
+#define ASM_OUTPUT_CHAR(FILE, VALUE)		\
+  do						\
+    {						\
+      fprintf (FILE, "\t.byte\t");		\
+      output_addr_const (FILE, (VALUE));	\
+      fprintf (FILE, "\n");			\
+    }						\
+  while (0)
 
 /* This is how to output an assembler line defining a `short' constant.  */
-#define ASM_OUTPUT_SHORT(FILE, VALUE) \
-do {						\
-  fprintf (FILE, "\t.hword\t");			\
-  output_addr_const (FILE, (VALUE));		\
-  fprintf (FILE, "\n");				\
-} while (0)
+#define ASM_OUTPUT_SHORT(FILE, VALUE)		\
+  do						\
+    {						\
+      fprintf (FILE, "\t.hword\t");		\
+      output_addr_const (FILE, (VALUE));	\
+      fprintf (FILE, "\n");			\
+    }						\
+  while (0)
 
 /* This is how to output an assembler line defining an `int' constant.
    We also handle symbol output here.  */
-#define ASM_OUTPUT_INT(FILE, VALUE) \
-do {							\
-  fprintf (FILE, "\t.word\t");				\
-  output_addr_const (FILE, (VALUE));			\
-  fprintf (FILE, "\n");					\
-} while (0)
+#define ASM_OUTPUT_INT(FILE, VALUE)		\
+  do						\
+    {						\
+      fprintf (FILE, "\t.word\t");		\
+      output_addr_const (FILE, (VALUE));	\
+      fprintf (FILE, "\n");			\
+    }						\
+  while (0)
 
 /* This is how to output an assembler line defining a `float' constant.  */
-#define ASM_OUTPUT_FLOAT(FILE, VALUE) \
-do {							\
-  long t;						\
-  char str[30];						\
-  REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);		\
-  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);	\
-  fprintf (FILE, "\t.word\t0x%lx %s %s\n",		\
-	   t, ASM_COMMENT_START, str);			\
-} while (0)
+#define ASM_OUTPUT_FLOAT(FILE, VALUE)			\
+  do							\
+    {							\
+      long t;						\
+      char str[30];					\
+      REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);		\
+      REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);	\
+      fprintf (FILE, "\t.word\t0x%lx %s %s\n",		\
+	       t, ASM_COMMENT_START, str);		\
+    }							\
+  while (0)
 
 /* This is how to output an assembler line defining a `double' constant.  */
-#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
-do {							\
-  long t[2];						\
-  char str[30];						\
-  REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);		\
-  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);	\
-  fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \
-	   t[0], ASM_COMMENT_START, str, t[1]);		\
-} while (0)
+#define ASM_OUTPUT_DOUBLE(FILE, VALUE)				\
+  do								\
+    {								\
+      long t[2];						\
+      char str[30];						\
+      REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);			\
+      REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);		\
+      fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n",	\
+	       t[0], ASM_COMMENT_START, str, t[1]);		\
+    }								\
+  while (0)
 
 /* This is how to output an assembler line for a numeric constant byte.  */
-#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
+#define ASM_OUTPUT_BYTE(FILE, VALUE)				\
   fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
 
 /* The assembler's parentheses characters.  */
@@ -1631,30 +1824,36 @@ do {							\
    such as the label on a static function or variable NAME.  */
 /* On the M32R we need to ensure the next instruction starts on a 32 bit
    boundary [the previous insn must either be 2 16 bit insns or 1 32 bit].  */
-#define ASM_OUTPUT_LABEL(FILE, NAME) \
-do {					\
-  assemble_name (FILE, NAME);		\
-  fputs (":\n", FILE);			\
-} while (0)
+#define ASM_OUTPUT_LABEL(FILE, NAME)	\
+  do					\
+    {					\
+      assemble_name (FILE, NAME);	\
+      fputs (":\n", FILE);		\
+    }					\
+  while (0)
 
 /* This is how to output a command to make the user-level label named NAME
    defined for reference from other files.  */
-#define ASM_GLOBALIZE_LABEL(FILE, NAME) \
-do {				\
-  fputs ("\t.global\t", FILE);	\
-  assemble_name (FILE, NAME);	\
-  fputs ("\n", FILE);		\
-} while (0)
+#define ASM_GLOBALIZE_LABEL(FILE, NAME)	\
+  do					\
+    {					\
+      fputs ("\t.global\t", FILE);	\
+      assemble_name (FILE, NAME);	\
+      fputs ("\n", FILE);		\
+    }					\
+  while (0)
 
 /* This is how to output a reference to a user-level label named NAME.
    `assemble_name' uses this.  */
-#undef ASM_OUTPUT_LABELREF
-#define ASM_OUTPUT_LABELREF(FILE, NAME) \
-do {							\
-  const char * real_name;				\
-  STRIP_NAME_ENCODING (real_name, (NAME));		\
-  asm_fprintf (FILE, "%U%s", real_name);		\
-} while (0)           
+#undef  ASM_OUTPUT_LABELREF
+#define ASM_OUTPUT_LABELREF(FILE, NAME) 	\
+  do						\
+    {						\
+      const char * real_name;			\
+      STRIP_NAME_ENCODING (real_name, (NAME));	\
+      asm_fprintf (FILE, "%U%s", real_name);	\
+    }						\
+  while (0)           
 
 /* If -Os, don't force line number labels to begin at the beginning of
    the word; we still want the assembler to try to put things in parallel,
@@ -1666,63 +1865,74 @@ do {							\
 
 #undef	ASM_OUTPUT_SOURCE_LINE
 #define ASM_OUTPUT_SOURCE_LINE(file, line)				\
-do									\
-  {									\
-    static int sym_lineno = 1;						\
-    fprintf (file, ".stabn 68,0,%d,.LM%d-",				\
-	     line, sym_lineno);						\
-    assemble_name (file,						\
-		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));\
-    fprintf (file,							\
-	     (optimize_size || TARGET_M32R)				\
-	     ? "\n\t.debugsym .LM%d\n"					\
-	     : "\n.LM%d:\n",						\
-	     sym_lineno);						\
-    sym_lineno += 1;							\
-  }									\
-while (0)
+  do									\
+    {									\
+      static int sym_lineno = 1;					\
+      fprintf (file, ".stabn 68,0,%d,.LM%d-",				\
+	       line, sym_lineno);					\
+      assemble_name							\
+	(file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));	\
+      fprintf (file, (optimize_size || TARGET_M32R)			\
+	       ? "\n\t.debugsym .LM%d\n"				\
+	       : "\n.LM%d:\n",						\
+	       sym_lineno);						\
+      sym_lineno += 1;							\
+    }									\
+  while (0)
 
 /* Store in OUTPUT a string (made with alloca) containing
    an assembler-name for a local static variable named NAME.
    LABELNO is an integer which is different for each call.  */
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-do {							\
-  (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10);	\
-  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO));	\
-} while (0)
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+  do							\
+    {							\
+      (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10);\
+      sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO));	\
+    }							\
+  while (0)
 
 /* How to refer to registers in assembler output.
    This sequence is indexed by compiler's hard-register-number (see above).  */
-#define REGISTER_NAMES \
+#ifndef SUBTARGET_REGISTER_NAMES
+#define SUBTARGET_REGISTER_NAMES
+#endif
+
+#define REGISTER_NAMES					\
 {							\
   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",	\
   "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",	\
-  "ap", "cbit"						\
+  "ap", "cbit", "a0"					\
+  SUBTARGET_REGISTER_NAMES				\
 }
 
 /* If defined, a C initializer for an array of structures containing
    a name and a register number.  This macro defines additional names
    for hard registers, thus allowing the `asm' option in declarations
    to refer to registers using alternate names.  */
-#define ADDITIONAL_REGISTER_NAMES \
+#ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES
+#define SUBTARGET_ADDITIONAL_REGISTER_NAMES
+#endif
+
+#define ADDITIONAL_REGISTER_NAMES	\
 {					\
   /*{ "gp", GP_REGNUM },*/		\
   { "r13", FRAME_POINTER_REGNUM },	\
   { "r14", RETURN_ADDR_REGNUM },	\
   { "r15", STACK_POINTER_REGNUM },	\
+  SUBTARGET_ADDITIONAL_REGISTER_NAMES	\
 }
 
 /* A C expression which evaluates to true if CODE is a valid
    punctuation character for use in the `PRINT_OPERAND' macro.  */
 extern char m32r_punct_chars[];
 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
-m32r_punct_chars[(unsigned char) (CHAR)]
+  m32r_punct_chars[(unsigned char) (CHAR)]
 
 /* Print operand X (an rtx) in assembler syntax to file FILE.
    CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
    For `%' followed by punctuation, CODE is the punctuation and X is null.  */
 #define PRINT_OPERAND(FILE, X, CODE) \
-m32r_print_operand (FILE, X, CODE)
+  m32r_print_operand (FILE, X, CODE)
 
 /* A C compound statement to output to stdio stream STREAM the
    assembler syntax for an instruction operand that is a memory
@@ -1733,7 +1943,7 @@ m32r_print_operand (FILE, X, CODE)
    define the macro `ENCODE_SECTION_INFO' to store the information
    into the `symbol_ref', and then check for it here.  */
 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-m32r_print_operand_address (FILE, ADDR)
+  m32r_print_operand_address (FILE, ADDR)
 
 /* If defined, C string expressions to be used for the `%R', `%L',
    `%U', and `%I' options of `asm_fprintf' (see `final.c').  These
@@ -1746,27 +1956,31 @@ m32r_print_operand_address (FILE, ADDR)
 #define IMMEDIATE_PREFIX "#"
 
 /* This is how to output an element of a case-vector that is absolute.  */
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
-do {							\
-  char label[30];					\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);	\
-  fprintf (FILE, "\t.word\t");				\
-  assemble_name (FILE, label);				\
-  fprintf (FILE, "\n");					\
-} while (0)
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)		\
+   do							\
+     {							\
+       char label[30];					\
+       ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);	\
+       fprintf (FILE, "\t.word\t");			\
+       assemble_name (FILE, label);			\
+       fprintf (FILE, "\n");				\
+     }							\
+  while (0)
 
 /* This is how to output an element of a case-vector that is relative.  */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
-do {							\
-  char label[30];					\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);	\
-  fprintf (FILE, "\t.word\t");				\
-  assemble_name (FILE, label);				\
-  fprintf (FILE, "-");					\
-  ASM_GENERATE_INTERNAL_LABEL (label, "L", REL);	\
-  assemble_name (FILE, label);				\
-  fprintf (FILE, ")\n");				\
-} while (0)
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\
+  do							\
+    {							\
+      char label[30];					\
+      ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);	\
+      fprintf (FILE, "\t.word\t");			\
+      assemble_name (FILE, label);			\
+      fprintf (FILE, "-");				\
+      ASM_GENERATE_INTERNAL_LABEL (label, "L", REL);	\
+      assemble_name (FILE, label);			\
+      fprintf (FILE, ")\n");				\
+    }							\
+  while (0)
 
 /* The desired alignment for the location counter at the beginning
    of a loop.  */
@@ -1774,12 +1988,27 @@ do {							\
    if -malign-loops.  */
 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
 
+/* Define this to be the maximum number of insns to move around when moving
+   a loop test from the top of a loop to the bottom
+   and seeing whether to duplicate it.  The default is thirty.
+
+   Loop unrolling currently doesn't like this optimization, so
+   disable doing if we are unrolling loops and saving space.  */
+#define LOOP_TEST_THRESHOLD (optimize_size				\
+			     && !flag_unroll_loops			\
+			     && !flag_unroll_all_loops ? 2 : 30)
+
 /* This is how to output an assembler line
    that says to advance the location counter
    to a multiple of 2**LOG bytes.  */
 /* .balign is used to avoid confusion.  */
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
-do { if ((LOG) != 0) fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); } while (0)
+#define ASM_OUTPUT_ALIGN(FILE,LOG)			\
+  do							\
+    {							\
+      if ((LOG) != 0)					\
+	fprintf (FILE, "\t.balign %d\n", 1 << (LOG));	\
+    }							\
+  while (0)
 
 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
    separate, explicit argument.  If you define this macro, it is used in
@@ -1789,51 +2018,19 @@ do { if ((LOG) != 0) fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); } while (0)
 
 #define SCOMMON_ASM_OP ".scomm"
 
-#undef ASM_OUTPUT_ALIGNED_COMMON
-#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
-do {									\
-  if (! TARGET_SDATA_NONE						\
-      && (SIZE) > 0 && (SIZE) <= g_switch_value)			\
-    fprintf ((FILE), "\t%s\t", SCOMMON_ASM_OP);				\
-  else									\
-    fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
-} while (0)
-
-#if 0 /* not needed, delete later */
-/* Like `ASM_OUTPUT_LOCAL' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used in
-   place of `ASM_OUTPUT_LOCAL', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.  */
-
-#undef ASM_OUTPUT_ALIGNED_LOCAL
-#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
-do {									\
-  if ((SIZE) > 0 && (SIZE) <= g_switch_value)				\
-    {									\
-      sbss_section ();							\
-      ASM_OUTPUT_ALIGN (FILE, exact_log2 (ALIGN / BITS_PER_UNIT));	\
-      ASM_OUTPUT_LABEL (FILE, NAME);					\
-      ASM_OUTPUT_SKIP (FILE, SIZE);					\
-      if (!flag_inhibit_size_directive)					\
-	{								\
-	  fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			\
-	  assemble_name (FILE, NAME);					\
-	  fprintf (FILE, ",%d\n",  SIZE);				\
-	}								\
-    }									\
-  else									\
+#undef  ASM_OUTPUT_ALIGNED_COMMON
+#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
+  do									\
     {									\
-      /* This is copied from svr4.h.  */				\
-      fprintf ((FILE), "\t%s\t", LOCAL_ASM_OP);				\
+      if (! TARGET_SDATA_NONE						\
+	  && (SIZE) > 0 && (SIZE) <= g_switch_value)			\
+	fprintf ((FILE), "\t%s\t", SCOMMON_ASM_OP);			\
+      else								\
+	fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);			\
       assemble_name ((FILE), (NAME));					\
-      fprintf ((FILE), "\n");						\
-      ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);		\
+      fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
     }									\
-} while (0)
-#endif
+  while (0)
 
 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
    separate, explicit argument.  If you define this macro, it is used in
@@ -1843,20 +2040,27 @@ do {									\
 
    For the M32R we need sbss support.  */
 
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-do {									\
-  ASM_GLOBALIZE_LABEL (FILE, NAME);					\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
-} while (0)
+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)	\
+  do								\
+    {								\
+      ASM_GLOBALIZE_LABEL (FILE, NAME);				\
+      ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);	\
+    }								\
+  while (0)
 
 /* Debugging information.  */
 
 /* Generate DBX and DWARF debugging information.  */
+#undef	DBX_DEBUGGING_INFO
+#undef	DWARF_DEBUGGING_INFO
+#undef	DWARF2_DEBUGGING_INFO
+
 #define DBX_DEBUGGING_INFO
 #define DWARF_DEBUGGING_INFO
+#define DWARF2_DEBUGGING_INFO
 
 /* Prefer STABS (for now).  */
-#undef PREFERRED_DEBUGGING_TYPE
+#undef  PREFERRED_DEBUGGING_TYPE
 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
 
 /* How to renumber registers for dbx and gdb.  */
@@ -1916,7 +2120,7 @@ do {									\
    After generation of rtl, the compiler makes no further distinction
    between pointers and any other objects of this machine mode.  */
 /* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
-   its own problems (you have to add extendpsisi2 and truncsipsi2).
+   it's own problems (you have to add extendpsisi2 and truncsipsi2).
    Try to avoid it.  */
 #define Pmode SImode
 
@@ -1933,11 +2137,11 @@ m32r_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
    incompatible, one if they are compatible, and two if they are
    nearly compatible (which causes a warning to be generated).  */
 #define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
-m32r_comp_type_attributes (TYPE1, TYPE2)
+  m32r_comp_type_attributes (TYPE1, TYPE2)
 
 /* Give newly defined TYPE some default attributes.  */
 #define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
-m32r_set_default_type_attributes (TYPE)
+  m32r_set_default_type_attributes (TYPE)
 
 /* Define the information needed to generate branch and scc insns.  This is
    stored from the compare operation.  Note that we can't use "rtx" here
@@ -1950,8 +2154,8 @@ enum m32r_function_type
 {
   M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
 };
-#define M32R_INTERRUPT_P(TYPE) \
-((TYPE) == M32R_FUNCTION_INTERRUPT)
+
+#define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT)
 
 /* Define this if you have defined special-purpose predicates in the
    file `MACHINE.c'.  This macro is called within an initializer of an
@@ -1973,97 +2177,19 @@ enum m32r_function_type
 				  CONST_DOUBLE }},			\
 { "two_insn_const_operand",	{ CONST_INT }},				\
 { "symbolic_operand",		{ SYMBOL_REF, LABEL_REF, CONST }},	\
+{ "seth_add3_operand",		{ SYMBOL_REF, LABEL_REF, CONST }},	\
+{ "int8_operand",		{ CONST_INT }},				\
+{ "uint16_operand",		{ CONST_INT }},				\
 { "reg_or_int16_operand",	{ REG, SUBREG, CONST_INT }},		\
 { "reg_or_uint16_operand",	{ REG, SUBREG, CONST_INT }},		\
 { "reg_or_cmp_int16_operand",	{ REG, SUBREG, CONST_INT }},		\
-{ "reg_or_zero_operand",	{ REG, SUBREG, CONST_INT }},		\
+{ "reg_or_eq_int16_operand",	{ REG, SUBREG, CONST_INT }},		\
 { "cmp_int16_operand",		{ CONST_INT }},				\
 { "call_address_operand",	{ SYMBOL_REF, LABEL_REF, CONST }},	\
+{ "extend_operand",		{ REG, SUBREG, MEM }},			\
 { "small_insn_p",		{ INSN, CALL_INSN, JUMP_INSN }},	\
+{ "m32r_not_same_reg",		{ REG, SUBREG }},			\
 { "m32r_block_immediate_operand",{ CONST_INT }},			\
 { "large_insn_p",		{ INSN, CALL_INSN, JUMP_INSN }},	\
 { "seth_add3_operand",		{ SYMBOL_REF, LABEL_REF, CONST }},
 
-/* Functions declared in m32r.c */
-#define XPROTO(ARGS) ()
-#define STDIO_XPROTO(ARGS) ()
-
-#ifndef TREE_CODE
-union tree_node;
-#define Tree union tree_node *
-#else
-#define Tree tree
-#endif
-
-#ifndef RTX_CODE
-struct rtx_def;
-#define Rtx struct rtx_def *
-#else
-#define Rtx rtx
-#endif
-
-extern void sbss_section			XPROTO((void));
-extern void sdata_section			XPROTO((void));
-extern void m32r_init				XPROTO((void));
-extern int  m32r_valid_machine_decl_attribute	XPROTO((Tree, Tree, Tree, Tree));
-extern int  m32r_comp_type_attributes		XPROTO((Tree, Tree));
-extern void m32r_select_section			XPROTO((Tree, int));
-extern void m32r_encode_section_info		XPROTO((Tree));
-extern void m32r_init_expanders			XPROTO((void));
-extern int  call_address_operand		XPROTO((Rtx, enum machine_mode));
-extern int  call_operand			XPROTO((Rtx, enum machine_mode));
-extern int  symbolic_operand			XPROTO((Rtx, enum machine_mode));
-extern int  small_data_operand			XPROTO((Rtx, enum machine_mode));
-extern int  addr24_operand			XPROTO((Rtx, enum machine_mode));
-extern int  addr32_operand			XPROTO((Rtx, enum machine_mode));
-extern int  call26_operand			XPROTO((Rtx, enum machine_mode));
-extern int  seth_add3_operand			XPROTO((Rtx, enum machine_mode));
-extern int  cmp_int16_operand			XPROTO((Rtx, enum machine_mode));
-extern int  uint16_operand			XPROTO((Rtx, enum machine_mode));
-extern int  reg_or_int16_operand		XPROTO((Rtx, enum machine_mode));
-extern int  reg_or_uint16_operand		XPROTO((Rtx, enum machine_mode));
-extern int  reg_or_cmp_nt16_operand		XPROTO((Rtx, enum machine_mode));
-extern int  two_insn_const_operand		XPROTO((Rtx, enum machine_mode));
-extern int  move_src_operand			XPROTO((Rtx, enum machine_mode));
-extern int  move_double_src_operand		XPROTO((Rtx, enum machine_mode));
-extern int  move_dest_operand			XPROTO((Rtx, enum machine_mode));
-extern int  easy_di_const			XPROTO((Rtx));
-extern int  easy_df_const			XPROTO((Rtx));
-extern int  eqne_comparison_operator		XPROTO((Rtx, enum machine_mode));
-extern int  signed_comparison_operator		XPROTO((Rtx, enum machine_mode));
-extern int  memreg_operand			XPROTO((Rtx, enum machine_mode));
-extern int  small_insn_p			XPROTO((Rtx, enum machine_mode));
-extern int  large_insn_p			XPROTO((Rtx, enum machine_mode));
-extern int  m32r_select_cc_mode			XPROTO((int, Rtx, Rtx));
-extern Rtx  gen_compare				XPROTO((int, Rtx, Rtx, int));
-extern Rtx  gen_split_move_double		XPROTO((Rtx *));
-extern int  function_arg_partial_nregs		XPROTO((CUMULATIVE_ARGS *,
-						       int, Tree, int));
-extern void m32r_setup_incoming_varargs		XPROTO((CUMULATIVE_ARGS *,
-						       int, Tree, int *,
-						       int));
-extern struct rtx_def *m32r_va_arg		XPROTO((Tree, Tree));
-extern int  m32r_address_code			XPROTO((Rtx));
-extern enum m32r_function_type m32r_compute_function_type
-						XPROTO((Tree));
-extern unsigned m32r_compute_frame_size		XPROTO((int));
-extern int  m32r_first_insn_address		XPROTO((void));
-extern void m32r_expand_prologue		XPROTO((void));
-extern void m32r_output_function_prologue	STDIO_XPROTO((FILE *, int));
-extern void m32r_output_function_epilogue	STDIO_XPROTO((FILE *, int));
-extern void m32r_finalize_pic			XPROTO((void));
-extern void m32r_initialize_trampoline		XPROTO((Rtx, Rtx, Rtx));
-extern void m32r_asm_file_start			STDIO_XPROTO((FILE *));
-extern void m32r_print_operand			STDIO_XPROTO((FILE *, Rtx, int));
-extern void m32r_print_operand_address		STDIO_XPROTO((FILE *, Rtx));
-extern int  zero_and_one			XPROTO((Rtx, Rtx));
-extern int  conditional_move_operand		XPROTO((Rtx, enum machine_mode));
-extern int  carry_compare_operand		XPROTO((Rtx, enum machine_mode));
-extern char *emit_cond_move			XPROTO((Rtx *, Rtx));
-
-extern char * m32r_output_block_move XPROTO((Rtx, Rtx *));
-extern int    m32r_block_immediate_operand XPROTO((Rtx, enum machine_mode));
-extern void   m32r_expand_block_move XPROTO((Rtx *));
-
-#undef XPROTO
-#undef STDIO_XPROTO
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index 0ad11f0..57ca196 100644
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -69,8 +69,6 @@
 (define_attr "m32r" "no,yes"
   (const (symbol_ref "(TARGET_M32R != 0)")))
 
-
-
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -220,10 +218,6 @@
   3 0
   [(eq_attr "insn_size" "short")])
 
-
-
-;; Instruction grouping
-
 
 ;; Expand prologue as RTL
 (define_expand "prologue"
@@ -340,7 +334,7 @@
 
 ;; ??? Do we need a const_double constraint here for large unsigned values?
 (define_insn "*movsi_insn"
-  [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,U,m")
+  [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,r,r,T,S,m")
 	(match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,n,T,U,m,r,r,r"))]
   "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
   "*
@@ -359,6 +353,10 @@
 	    return \"mv %0,%1\";
 
 	  case MEM:
+	    if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
+		&& XEXP (XEXP (operands[1], 0), 0) == stack_pointer_rtx)
+	      return \"pop %0\";
+
 	    return \"ld %0,%1\";
 
 	  case CONST_INT:
@@ -386,7 +384,13 @@
 
   else if (GET_CODE (operands[0]) == MEM
 	   && (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG))
-    return \"st %1,%0\";
+    {
+      if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
+	  && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
+	return \"push %1\";
+
+      return \"st %1,%0\";
+    }
 
   abort ();
 }"
@@ -568,19 +572,21 @@
 }")
 
 (define_insn "*movsf_insn"
-  [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,T,m")
-	(match_operand:SF 1 "move_src_operand" "r,F,T,m,r,r"))]
+  [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,r,r,T,S,m")
+	(match_operand:SF 1 "move_src_operand" "r,F,U,S,m,r,r,r"))]
   "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
   "@
    mv %0,%1
    #
    ld %0,%1
    ld %0,%1
+   ld %0,%1
+   st %1,%0
    st %1,%0
    st %1,%0"
   ;; ??? Length of alternative 1 is either 2, 4 or 8.
-  [(set_attr "type" "int2,multi,load2,load4,store2,store4")
-   (set_attr "length" "2,8,2,4,2,4")])
+  [(set_attr "type" "int2,multi,load2,load2,load4,store2,store2,store4")
+   (set_attr "length" "2,8,2,2,4,2,2,4")])
 
 (define_split
   [(set (match_operand:SF 0 "register_operand" "")
@@ -624,7 +630,7 @@
 
 (define_insn "zero_extendqihi2"
   [(set (match_operand:HI 0 "register_operand" "=r,r,r")
-	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,T,m")))]
+	(zero_extend:HI (match_operand:QI 1 "extend_operand" "r,T,m")))]
   ""
   "@
    and3 %0,%1,%#255
@@ -635,7 +641,7 @@
 
 (define_insn "zero_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,T,m")))]
+	(zero_extend:SI (match_operand:QI 1 "extend_operand" "r,T,m")))]
   ""
   "@
    and3 %0,%1,%#255
@@ -646,7 +652,7 @@
 
 (define_insn "zero_extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
-	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,T,m")))]
+	(zero_extend:SI (match_operand:HI 1 "extend_operand" "r,T,m")))]
   ""
   "@
    and3 %0,%1,%#65535
@@ -655,111 +661,84 @@
   [(set_attr "type" "int4,load2,load4")
    (set_attr "length" "4,2,4")])
 
-;; Sign extension instructions.
-;; ??? See v850.md.
-
-;; These patterns originally accepted general_operands, however, slightly
-;; better code is generated by only accepting register_operands, and then
-;; letting combine generate the lds[hb] insns.
-;; [This comment copied from sparc.md, I think.]
+;; Signed conversions from a smaller integer to a larger integer
+(define_insn "extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+	(sign_extend:HI (match_operand:QI 1 "extend_operand" "0,T,m")))]
+  ""
+  "@
+    #
+    ldb %0,%1
+    ldb %0,%1"
+  [(set_attr "type" "multi,load2,load4")
+   (set_attr "length" "2,2,4")])
 
-(define_expand "extendqihi2"
+(define_split
   [(set (match_operand:HI 0 "register_operand" "")
 	(sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
-  ""
+  "reload_completed"
+  [(match_dup 2)
+   (match_dup 3)]
   "
 {
-  rtx temp = gen_reg_rtx (SImode);
-  rtx shift_24 = GEN_INT (24);
-  int op1_subword = 0;
-  int op0_subword = 0;
+  rtx op0   = gen_lowpart (SImode, operands[0]);
+  rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
 
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-  if (GET_CODE (operand0) == SUBREG)
-    {
-      op0_subword = SUBREG_WORD (operand0);
-      operand0 = XEXP (operand0, 0);
-    }
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1,
-						op1_subword),
-			  shift_24));
-  if (GET_MODE (operand0) != SImode)
-    operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subword);
-  emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
-  DONE;
+  operands[2] = gen_ashlsi3 (op0, op0, shift);
+  operands[3] = gen_ashrsi3 (op0, op0, shift);
 }")
 
-(define_insn "*sign_extendqihi2_insn"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(sign_extend:HI (match_operand:QI 1 "memory_operand" "T,m")))]
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(sign_extend:SI (match_operand:QI 1 "extend_operand" "0,T,m")))]
   ""
-  "ldb %0,%1"
-  [(set_attr "type" "load2,load4")
-   (set_attr "length" "2,4")])
+  "@
+    #
+    ldb %0,%1
+    ldb %0,%1"
+  [(set_attr "type" "multi,load2,load4")
+   (set_attr "length" "4,2,4")])
 
-(define_expand "extendqisi2"
+(define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
-  ""
+  "reload_completed"
+  [(match_dup 2)
+   (match_dup 3)]
   "
 {
-  rtx temp = gen_reg_rtx (SImode);
-  rtx shift_24 = GEN_INT (24);
-  int op1_subword = 0;
-
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
+  rtx op0   = gen_lowpart (SImode, operands[0]);
+  rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
 
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword),
-			  shift_24));
-  emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
-  DONE;
+  operands[2] = gen_ashlsi3 (op0, op0, shift);
+  operands[3] = gen_ashrsi3 (op0, op0, shift);
 }")
 
-(define_insn "*sign_extendqisi2_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:QI 1 "memory_operand" "T,m")))]
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(sign_extend:SI (match_operand:HI 1 "extend_operand" "0,T,m")))]
   ""
-  "ldb %0,%1"
-  [(set_attr "type" "load2,load4")
-   (set_attr "length" "2,4")])
+  "@
+    #
+    ldh %0,%1
+    ldh %0,%1"
+  [(set_attr "type" "multi,load2,load4")
+   (set_attr "length" "4,2,4")])
 
-(define_expand "extendhisi2"
+(define_split
   [(set (match_operand:SI 0 "register_operand" "")
 	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
-  ""
+  "reload_completed"
+  [(match_dup 2)
+   (match_dup 3)]
   "
 {
-  rtx temp = gen_reg_rtx (SImode);
-  rtx shift_16 = GEN_INT (16);
-  int op1_subword = 0;
+  rtx op0   = gen_lowpart (SImode, operands[0]);
+  rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);
 
-  if (GET_CODE (operand1) == SUBREG)
-    {
-      op1_subword = SUBREG_WORD (operand1);
-      operand1 = XEXP (operand1, 0);
-    }
-
-  emit_insn (gen_ashlsi3 (temp, gen_rtx_SUBREG (SImode, operand1, op1_subword),
-			  shift_16));
-  emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
-  DONE;
+  operands[2] = gen_ashlsi3 (op0, op0, shift);
+  operands[3] = gen_ashrsi3 (op0, op0, shift);
 }")
-
-(define_insn "*sign_extendhisi2_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(sign_extend:SI (match_operand:HI 1 "memory_operand" "T,m")))]
-  ""
-  "ldh %0,%1"
-  [(set_attr "type" "load2,load4")
-   (set_attr "length" "2,4")])
 
 ;; Arithmetic instructions.
 
@@ -977,36 +956,99 @@
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(and:SI (match_operand:SI 1 "register_operand" "%0,r")
-		(match_operand:SI 2 "nonmemory_operand" "r,K")))]
+		(match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
   ""
-  "@
-   and %0,%2
-   and3 %0,%1,%#%2\\t; %X2"
+  "*
+{
+  /* If we are worried about space, see if we can break this up into two
+     short instructions, which might eliminate a NOP being inserted.  */
+  if (optimize_size
+      && m32r_not_same_reg (operands[0], operands[1])
+      && GET_CODE (operands[2]) == CONST_INT
+      && INT8_P (INTVAL (operands[2])))
+    return \"#\";
+
+  else if (GET_CODE (operands[2]) == CONST_INT)
+    return \"and3 %0,%1,%#%X2\";
+
+  return \"and %0,%2\";
+}"
   [(set_attr "type" "int2,int4")
    (set_attr "length" "2,4")])
 
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(and:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "int8_operand" "")))]
+  "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
+  [(set (match_dup 0) (match_dup 2))
+   (set (match_dup 0) (and:SI (match_dup 1) (match_dup 0)))]
+  "")
+
 (define_insn "iorsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(ior:SI (match_operand:SI 1 "register_operand" "%0,r")
-		(match_operand:SI 2 "nonmemory_operand" "r,K")))]
+		(match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
   ""
-  "@
-   or %0,%2
-   or3 %0,%1,%#%2\\t; %X2"
+  "*
+{
+  /* If we are worried about space, see if we can break this up into two
+     short instructions, which might eliminate a NOP being inserted.  */
+  if (optimize_size
+      && m32r_not_same_reg (operands[0], operands[1])
+      && GET_CODE (operands[2]) == CONST_INT
+      && INT8_P (INTVAL (operands[2])))
+    return \"#\";
+
+  else if (GET_CODE (operands[2]) == CONST_INT)
+    return \"or3 %0,%1,%#%X2\";
+
+  return \"or %0,%2\";
+}"
   [(set_attr "type" "int2,int4")
    (set_attr "length" "2,4")])
 
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ior:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "int8_operand" "")))]
+  "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
+  [(set (match_dup 0) (match_dup 2))
+   (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 0)))]
+  "")
+
 (define_insn "xorsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
 	(xor:SI (match_operand:SI 1 "register_operand" "%0,r")
-		(match_operand:SI 2 "nonmemory_operand" "r,K")))]
+		(match_operand:SI 2 "reg_or_uint16_operand" "r,K")))]
   ""
-  "@
-   xor %0,%2
-   xor3 %0,%1,%#%2\\t; %X2"
+  "*
+{
+  /* If we are worried about space, see if we can break this up into two
+     short instructions, which might eliminate a NOP being inserted.  */
+  if (optimize_size
+      && m32r_not_same_reg (operands[0], operands[1])
+      && GET_CODE (operands[2]) == CONST_INT
+      && INT8_P (INTVAL (operands[2])))
+    return \"#\";
+
+  else if (GET_CODE (operands[2]) == CONST_INT)
+    return \"xor3 %0,%1,%#%X2\";
+
+  return \"xor %0,%2\";
+}"
   [(set_attr "type" "int2,int4")
    (set_attr "length" "2,4")])
 
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(xor:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "int8_operand" "")))]
+  "optimize_size && m32r_not_same_reg (operands[0], operands[1])"
+  [(set (match_dup 0) (match_dup 2))
+   (set (match_dup 0) (xor:SI (match_dup 1) (match_dup 0)))]
+  "")
+
 (define_insn "negsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
@@ -1074,8 +1116,8 @@
 
 (define_expand "cmpsi"
   [(set (reg:SI 17)
-	(compare:SI (match_operand:SI 0 "register_operand" "")
-		    (match_operand:SI 1 "nonmemory_operand" "")))]
+	(compare:CC (match_operand:SI 0 "register_operand" "")
+		    (match_operand:SI 1 "reg_or_cmp_int16_operand" "")))]
   ""
   "
 {
@@ -1084,7 +1126,6 @@
   DONE;
 }")
 
-
 ;; The cmp_xxx_insn patterns set the condition bit to the result of the
 ;; comparison.  There isn't a "compare equal" instruction so cmp_eqsi_insn
 ;; is quite inefficient.  However, it is rarely used.
@@ -1128,7 +1169,7 @@
 (define_insn "cmp_ltusi_insn"
   [(set (reg:SI 17)
 	(ltu:SI (match_operand:SI 0 "register_operand" "r,r")
-	        (match_operand:SI 1 "reg_or_uint16_operand" "r,K")))]
+	        (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
   ""
   "@
    cmpu %0,%1
@@ -1162,7 +1203,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)EQ, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "bne"
@@ -1173,7 +1214,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)NE, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "bgt"
@@ -1184,7 +1225,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)GT, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "ble"
@@ -1195,7 +1236,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)LE, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "bge"
@@ -1206,7 +1247,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)GE, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "blt"
@@ -1217,7 +1258,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)LT, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "bgtu"
@@ -1228,7 +1269,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)GTU, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "bleu"
@@ -1239,7 +1280,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)LEU, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "bgeu"
@@ -1250,7 +1291,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)GEU, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 (define_expand "bltu"
@@ -1261,7 +1302,7 @@
   ""
   "
 {
-  operands[1] = gen_compare ((int)LTU, m32r_compare_op0, m32r_compare_op1, FALSE);
+  operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1, FALSE);
 }")
 
 ;; Now match both normal and inverted jump.
@@ -1491,6 +1532,636 @@
 				      (const_int 4)
 				      (const_int 8)))])
 
+;; S<cc> operations to set a register to 1/0 based on a comparison
+
+(define_expand "seq"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (! register_operand (op1, mode))
+    op1 = force_reg (mode, op1);
+
+  if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
+    {
+      emit_insn (gen_seq_zero_insn (op0, op1));
+      DONE;
+    }
+
+  if (! reg_or_eq_int16_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_seq_insn (op0, op1, op2));
+  DONE;
+}")
+
+(define_insn "seq_zero_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(eq:SI (match_operand:SI 1 "register_operand" "r")
+	       (const_int 0)))
+   (clobber (reg:SI 17))]
+  "TARGET_M32R"
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "6")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(eq:SI (match_operand:SI 1 "register_operand" "")
+	       (const_int 0)))
+   (clobber (reg:SI 17))]
+  "TARGET_M32R"
+  [(match_dup 3)]
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+
+  start_sequence ();
+  emit_insn (gen_cmp_ltusi_insn (op1, GEN_INT (1)));
+  emit_insn (gen_movcc_insn (op0));
+  operands[3] = gen_sequence ();
+  end_sequence ();
+}")
+
+(define_insn "seq_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,??r,r")
+	(eq:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
+	       (match_operand:SI 2 "reg_or_eq_int16_operand" "r,r,r,PK")))
+   (clobber (reg:SI 17))
+   (clobber (match_scratch:SI 3 "=1,2,&r,r"))]
+  "TARGET_M32R"
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "8,8,10,10")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(eq:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "reg_or_eq_int16_operand" "")))
+   (clobber (reg:SI 17))
+   (clobber (match_scratch:SI 3 ""))]
+  "TARGET_M32R && reload_completed"
+  [(match_dup 4)]
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  rtx op2 = operands[2];
+  rtx op3 = operands[3];
+  HOST_WIDE_INT value;
+
+  if (GET_CODE (op2) == REG && GET_CODE (op3) == REG
+      && REGNO (op2) == REGNO (op3))
+    {
+      op1 = operands[2];
+      op2 = operands[1];
+    }
+
+  start_sequence ();
+  if (GET_CODE (op1) == REG && GET_CODE (op3) == REG
+      && REGNO (op1) != REGNO (op3))
+    {
+      emit_move_insn (op3, op1);
+      op1 = op3;
+    }
+
+  if (GET_CODE (op2) == CONST_INT && (value = INTVAL (op2)) != 0
+      && CMP_INT16_P (value))
+    emit_insn (gen_addsi3 (op3, op1, GEN_INT (-value)));
+  else
+    emit_insn (gen_xorsi3 (op3, op1, op2));
+
+  emit_insn (gen_cmp_ltusi_insn (op3, GEN_INT (1)));
+  emit_insn (gen_movcc_insn (op0));
+  operands[4] = gen_sequence ();
+  end_sequence ();
+}")
+
+(define_expand "sne"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (GET_CODE (op2) != CONST_INT
+      || (INTVAL (op2) != 0 && UINT16_P (INTVAL (op2))))
+    {
+      rtx reg;
+
+      if (reload_completed || reload_in_progress)
+	FAIL;
+
+      reg = gen_reg_rtx (SImode);
+      emit_insn (gen_xorsi3 (reg, op1, op2));
+      op1 = reg;
+
+      if (! register_operand (op1, mode))
+        op1 = force_reg (mode, op1);
+
+      emit_insn (gen_sne_zero_insn (op0, op1));
+      DONE;
+    }
+  else
+    FAIL;
+}")
+
+(define_insn "sne_zero_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ne:SI (match_operand:SI 1 "register_operand" "r")
+	       (const_int 0)))
+   (clobber (reg:SI 17))
+   (clobber (match_scratch:SI 2 "=&r"))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "6")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ne:SI (match_operand:SI 1 "register_operand" "")
+	       (const_int 0)))
+   (clobber (reg:SI 17))
+   (clobber (match_scratch:SI 2 ""))]
+  "reload_completed"
+  [(set (match_dup 2)
+	(const_int 0))
+   (set (reg:SI 17)
+	(ltu:SI (match_dup 2)
+		(match_dup 1)))
+   (set (match_dup 0)
+	(reg:SI 17))]
+  "")
+	
+(define_expand "slt"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (! register_operand (op1, mode))
+    op1 = force_reg (mode, op1);
+
+  if (! reg_or_int16_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_slt_insn (op0, op1, op2));
+  DONE;
+}")
+
+(define_insn "slt_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(lt:SI (match_operand:SI 1 "register_operand" "r,r")
+	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
+   (clobber (reg:SI 17))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "4,6")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(lt:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "reg_or_int16_operand" "")))
+   (clobber (reg:SI 17))]
+  ""
+  [(set (reg:SI 17)
+	(lt:SI (match_dup 1)
+	       (match_dup 2)))
+   (set (match_dup 0)
+	(reg:SI 17))]
+  "")
+
+(define_expand "sle"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (! register_operand (op1, mode))
+    op1 = force_reg (mode, op1);
+
+  if (GET_CODE (op2) == CONST_INT)
+    {
+      HOST_WIDE_INT value = INTVAL (op2);
+      if (value >= 2147483647)
+	{
+	  emit_move_insn (op0, GEN_INT (1));
+	  DONE;
+	}
+
+      op2 = GEN_INT (value+1);
+      if (value < -32768 || value >= 32767)
+	op2 = force_reg (mode, op2);
+
+      emit_insn (gen_slt_insn (op0, op1, op2));
+      DONE;
+    }
+
+  if (! register_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_sle_insn (op0, op1, op2));
+  DONE;
+}")
+
+(define_insn "sle_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(le:SI (match_operand:SI 1 "register_operand" "r")
+	       (match_operand:SI 2 "register_operand" "r")))
+   (clobber (reg:SI 17))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(le:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "register_operand" "")))
+   (clobber (reg:SI 17))]
+  "!optimize_size"
+  [(set (reg:SI 17)
+	(lt:SI (match_dup 2)
+	       (match_dup 1)))
+   (set (match_dup 0)
+	(reg:SI 17))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
+;; xor reg,reg,1 which might eliminate a NOP being inserted.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(le:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "register_operand" "")))
+   (clobber (reg:SI 17))]
+  "optimize_size"
+  [(set (reg:SI 17)
+	(lt:SI (match_dup 2)
+	       (match_dup 1)))
+   (set (match_dup 0)
+	(reg:SI 17))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0)
+		 (const_int -1)))
+   (set (match_dup 0)
+	(neg:SI (match_dup 0)))]
+  "")
+
+(define_expand "sgt"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (! register_operand (op1, mode))
+    op1 = force_reg (mode, op1);
+
+  if (! register_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_slt_insn (op0, op2, op1));
+  DONE;
+}")
+
+(define_expand "sge"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (! register_operand (op1, mode))
+    op1 = force_reg (mode, op1);
+
+  if (! reg_or_int16_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_sge_insn (op0, op1, op2));
+  DONE;
+}")
+
+(define_insn "sge_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(ge:SI (match_operand:SI 1 "register_operand" "r,r")
+	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
+   (clobber (reg:SI 17))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "8,10")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ge:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "reg_or_int16_operand" "")))
+   (clobber (reg:SI 17))]
+  "!optimize_size"
+  [(set (reg:SI 17)
+	(lt:SI (match_dup 1)
+	       (match_dup 2)))
+   (set (match_dup 0)
+	(reg:SI 17))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
+;; xor reg,reg,1 which might eliminate a NOP being inserted.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ge:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "reg_or_int16_operand" "")))
+   (clobber (reg:SI 17))]
+  "optimize_size"
+  [(set (reg:SI 17)
+	(lt:SI (match_dup 1)
+	       (match_dup 2)))
+   (set (match_dup 0)
+	(reg:SI 17))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0)
+		 (const_int -1)))
+   (set (match_dup 0)
+	(neg:SI (match_dup 0)))]
+  "")
+
+(define_expand "sltu"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (! register_operand (op1, mode))
+    op1 = force_reg (mode, op1);
+
+  if (! reg_or_int16_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_sltu_insn (op0, op1, op2));
+  DONE;
+}")
+
+(define_insn "sltu_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(ltu:SI (match_operand:SI 1 "register_operand" "r,r")
+		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
+   (clobber (reg:SI 17))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "6,8")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(ltu:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "reg_or_int16_operand" "")))
+   (clobber (reg:SI 17))]
+  ""
+  [(set (reg:SI 17)
+	(ltu:SI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(reg:SI 17))]
+  "")
+
+(define_expand "sleu"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (GET_CODE (op2) == CONST_INT)
+    {
+      HOST_WIDE_INT value = INTVAL (op2);
+      if (value >= 2147483647)
+	{
+	  emit_move_insn (op0, GEN_INT (1));
+	  DONE;
+	}
+
+      op2 = GEN_INT (value+1);
+      if (value < 0 || value >= 32767)
+	op2 = force_reg (mode, op2);
+
+      emit_insn (gen_sltu_insn (op0, op1, op2));
+      DONE;
+    }
+
+  if (! register_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_sleu_insn (op0, op1, op2));
+  DONE;
+}")
+
+(define_insn "sleu_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(leu:SI (match_operand:SI 1 "register_operand" "r")
+		(match_operand:SI 2 "register_operand" "r")))
+   (clobber (reg:SI 17))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(leu:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "register_operand" "")))
+   (clobber (reg:SI 17))]
+  "!optimize_size"
+  [(set (reg:SI 17)
+	(ltu:SI (match_dup 2)
+		(match_dup 1)))
+   (set (match_dup 0)
+	(reg:SI 17))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
+;; xor reg,reg,1 which might eliminate a NOP being inserted.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(leu:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "register_operand" "")))
+   (clobber (reg:SI 17))]
+  "optimize_size"
+  [(set (reg:SI 17)
+	(ltu:SI (match_dup 2)
+		(match_dup 1)))
+   (set (match_dup 0)
+	(reg:SI 17))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0)
+		 (const_int -1)))
+   (set (match_dup 0)
+	(neg:SI (match_dup 0)))]
+  "")
+
+(define_expand "sgtu"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (! register_operand (op1, mode))
+    op1 = force_reg (mode, op1);
+
+  if (! register_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_sltu_insn (op0, op2, op1));
+  DONE;
+}")
+
+(define_expand "sgeu"
+  [(match_operand:SI 0 "register_operand" "")]
+  ""
+  "
+{
+  rtx op0 = operands[0];
+  rtx op1 = m32r_compare_op0;
+  rtx op2 = m32r_compare_op1;
+  enum machine_mode mode = GET_MODE (op0);
+
+  if (mode != SImode)
+    FAIL;
+
+  if (! register_operand (op1, mode))
+    op1 = force_reg (mode, op1);
+
+  if (! reg_or_int16_operand (op2, mode))
+    op2 = force_reg (mode, op2);
+
+  emit_insn (gen_sgeu_insn (op0, op1, op2));
+  DONE;
+}")
+
+(define_insn "sgeu_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(geu:SI (match_operand:SI 1 "register_operand" "r,r")
+		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
+   (clobber (reg:SI 17))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "8,10")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(geu:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "reg_or_int16_operand" "")))
+   (clobber (reg:SI 17))]
+  "!optimize_size"
+  [(set (reg:SI 17)
+	(ltu:SI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(reg:SI 17))
+   (set (match_dup 0)
+	(xor:SI (match_dup 0)
+		(const_int 1)))]
+  "")
+
+;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
+;; xor reg,reg,1 which might eliminate a NOP being inserted.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(geu:SI (match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "reg_or_int16_operand" "")))
+   (clobber (reg:SI 17))]
+  "optimize_size"
+  [(set (reg:SI 17)
+	(ltu:SI (match_dup 1)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(reg:SI 17))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0)
+		 (const_int -1)))
+   (set (match_dup 0)
+	(neg:SI (match_dup 0)))]
+  "")
+
+(define_insn "movcc_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(reg:SI 17))]
+  ""
+  "mvfc %0, cbr"
+  [(set_attr "type" "misc")
+   (set_attr "length" "2")])
+
+
 ;; Unconditional and other jump instructions.
 
 (define_insn "jump"
@@ -1510,6 +2181,13 @@
   "jmp %a0"
   [(set_attr "type" "uncond_branch")
    (set_attr "length" "2")])
+
+(define_insn "return"
+  [(return)]
+  "direct_return ()"
+  "jmp lr"
+  [(set_attr "type" "uncond_branch")
+   (set_attr "length" "2")])
  
 (define_insn "tablejump"
   [(set (pc) (match_operand:SI 0 "address_operand" "p"))
@@ -1646,10 +2324,51 @@
   [(set_attr "type" "int2")
    (set_attr "length" "2")])
 
+;; Speed up fabs and provide correct sign handling for -0
+
+(define_insn "absdf2"
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(abs:DF (match_operand:DF 1 "register_operand" "0")))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "4")])
+
+(define_split
+  [(set (match_operand:DF 0 "register_operand" "")
+	(abs:DF (match_operand:DF 1 "register_operand" "")))]
+  "reload_completed"
+  [(set (match_dup 2)
+	(ashift:SI (match_dup 2)
+		   (const_int 1)))
+   (set (match_dup 2)
+	(lshiftrt:SI (match_dup 2)
+		     (const_int 1)))]
+  "operands[2] = gen_highpart (SImode, operands[0]);")
+
+(define_insn "abssf2"
+  [(set (match_operand:SF 0 "register_operand" "=r")
+	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
+  ""
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "4")])
+
+(define_split
+  [(set (match_operand:SF 0 "register_operand" "")
+	(abs:SF (match_operand:SF 1 "register_operand" "")))]
+  "reload_completed"
+  [(set (match_dup 2)
+	(ashift:SI (match_dup 2)
+		   (const_int 1)))
+   (set (match_dup 2)
+	(lshiftrt:SI (match_dup 2)
+		     (const_int 1)))]
+  "operands[2] = gen_highpart (SImode, operands[0]);")
+
 ;; Conditional move instructions
 ;; Based on those done for the d10v
 
-
 (define_expand "movsicc"
   [
    (set (match_operand:SI 0 "register_operand" "r")
@@ -1666,11 +2385,11 @@
     FAIL;
 
   /* Generate the comparision that will set the carry flag.  */
-  operands[1] = gen_compare ((int)GET_CODE (operands[1]), m32r_compare_op0,
+  operands[1] = gen_compare (GET_CODE (operands[1]), m32r_compare_op0,
 			     m32r_compare_op1, TRUE);
 
   /* See other movsicc pattern below for reason why.  */
-  emit_insn (gen_blockage());
+  emit_insn (gen_blockage ());
 }")
 
 ;; Generate the conditional instructions based on how the carry flag is examined.
@@ -1688,19 +2407,9 @@
   ]
 )
 
-(define_insn "movcc_insn"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(reg:SI 17))]
-  ""
-  "mvfc %0, cbr"
-  [(set_attr "type" "misc")
-   (set_attr "length" "2")]
-)
-
 
 ;; Split up troublesome insns for better scheduling.
-
-;; Peepholes go at the end.
+;; FIXME: Peepholes go at the end.
 
 ;; ??? Setting the type attribute may not be useful, but for completeness
 ;; we do it.