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| author | Kazu Hirata <kazu@cs.umass.edu> | 2004-09-14 04:05:40 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@gcc.gnu.org> | 2004-09-14 04:05:40 +0000 |
| commit | 19525b57d1b46595e853e610669cd40f367f26e5 (patch) | |
| tree | 67f3a13e0d747fcade03caf5fdbb195186bd0681 /gcc/config/m32r/m32r.md | |
| parent | a140c081d1130e37116f5465d8db6eb58d7b0a60 (diff) | |
| download | gcc-19525b57d1b46595e853e610669cd40f367f26e5.zip gcc-19525b57d1b46595e853e610669cd40f367f26e5.tar.gz gcc-19525b57d1b46595e853e610669cd40f367f26e5.tar.bz2 | |
m32r.md, [...]: Fix comment typos.
* config/m32r/m32r.md, config/m68k/m68kelf.h,
config/mcore/mcore.md, config/rs6000/linux64.h,
config/rs6000/rs6000.c, config/sparc/sparc.c: Fix comment
typos.
From-SVN: r87481
Diffstat (limited to 'gcc/config/m32r/m32r.md')
| -rw-r--r-- | gcc/config/m32r/m32r.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index 8cd2679..f1236d4 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -169,7 +169,7 @@ ;; Load/store instructions do 6 stages: IF D E MEM1 MEM2 WB. ;; MEM1 may require more than one cycle depending on locality. We -;; optimistically assume all memory is nearby, ie. MEM1 takes only +;; optimistically assume all memory is nearby, i.e. MEM1 takes only ;; one cycle. Hence, ready latency is 3. ;; The M32Rx can do short load/store only on the left pipe. |