m32r.c: Add support for m32rx processor.

        * m32r.c: Add support for m32rx processor.
        * m32r.h: Ditto.
        * m32r.md: Ditto.
        * t-m32r: Ditto.
        * m32r-protos.h: Add prototypes for m32rx functions.
        * doc/invoke.texi: Document -m32rx option.

Co-Authored-By: Andrew MacLeod <amacleod@redhat.com>
Co-Authored-By: Catherine Moore <clm@redhat.com>
Co-Authored-By: Michael Meissner <meissner@redhat.com>
Co-Authored-By: Nick Clifton <nickc@redhat.com>
Co-Authored-By: Richard Henderson <rth@redhat.com>

From-SVN: r46881

1 files changed, 101 insertions, 8 deletions

diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index 5b8bac9..470a05d 100644
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -69,6 +69,26 @@
 (define_attr "m32r" "no,yes"
   (const (symbol_ref "(TARGET_M32R != 0)")))
 
+(define_attr "m32rx" "no,yes"
+  (const (symbol_ref "(TARGET_M32RX != 0)")))
+
+(define_attr "m32rx_pipeline" "either,s,o,long,m32r"
+  (cond [(eq_attr "m32rx" "no")
+         (const_string "m32r")
+
+         (eq_attr "insn_size" "!short")
+         (const_string "long")]
+
+        (cond [(eq_attr "type" "int2")
+               (const_string "either")
+
+               (eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")
+               (const_string "o")
+
+               (eq_attr "type" "mul2")
+               (const_string "s")]
+
+              (const_string "long"))))
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -218,6 +238,36 @@
   3 0
   [(eq_attr "insn_size" "short")])
 
+(define_function_unit "left" 1 1
+  (and (eq_attr "m32rx_pipeline" "o,either")
+       (eq_attr "type" "!load2"))
+  1 0
+  [(eq_attr "insn_size" "long")])
+
+(define_function_unit "left" 1 1	;; load delay of 1 clock for mem execution + 1 clock for WB
+  (and (eq_attr "m32rx_pipeline" "o,either")
+       (eq_attr "type" "load2"))
+  3 0
+  [(eq_attr "insn_size" "long")])
+
+(define_function_unit "right" 1 1
+  (eq_attr "m32rx_pipeline" "s,either")
+  1 0
+  [(eq_attr "insn_size" "long")])
+
+(define_function_unit "long" 1 1
+  (and (eq_attr "m32rx" "yes")
+       (and (eq_attr "insn_size" "long")
+	    (eq_attr "type" "!load4,load8")))
+  2 0
+  [(eq_attr "insn_size" "short")])
+
+(define_function_unit "long" 1 1	;; load delay of 1 clock for mem execution + 1 clock for WB
+  (and (eq_attr "m32rx" "yes")
+       (and (eq_attr "insn_size" "long")
+	    (eq_attr "type" "load4,load8")))
+  3 0
+  [(eq_attr "insn_size" "short")])
 
 ;; Expand prologue as RTL
 (define_expand "prologue"
@@ -1126,14 +1176,25 @@
   DONE;
 }")
 
+(define_insn "cmp_eqsi_zero_insn"
+  [(set (reg:SI 17)
+        (eq:SI (match_operand:SI 0 "register_operand" "r,r")
+               (match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
+  "TARGET_M32RX"
+  "@
+   cmpeq %0, %1
+   cmpz  %0"
+  [(set_attr "type" "int4")
+   (set_attr "length" "4")])
+
 ;; The cmp_xxx_insn patterns set the condition bit to the result of the
 ;; comparison.  There isn't a "compare equal" instruction so cmp_eqsi_insn
 ;; is quite inefficient.  However, it is rarely used.
 
 (define_insn "cmp_eqsi_insn"
   [(set (reg:SI 17)
-	(eq:SI (match_operand:SI 0 "register_operand" "r,r")
-	       (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
+        (eq:SI (match_operand:SI 0 "register_operand" "r,r")
+               (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
    (clobber (match_scratch:SI 2 "=&r,&r"))]
   ""
   "*
@@ -1157,8 +1218,8 @@
 
 (define_insn "cmp_ltsi_insn"
   [(set (reg:SI 17)
-	(lt:SI (match_operand:SI 0 "register_operand" "r,r")
-	       (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
+        (lt:SI (match_operand:SI 0 "register_operand" "r,r")
+               (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
   ""
   "@
    cmp %0,%1
@@ -1168,8 +1229,8 @@
 
 (define_insn "cmp_ltusi_insn"
   [(set (reg:SI 17)
-	(ltu:SI (match_operand:SI 0 "register_operand" "r,r")
-	        (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
+        (ltu:SI (match_operand:SI 0 "register_operand" "r,r")
+                (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
   ""
   "@
    cmpu %0,%1
@@ -1177,6 +1238,7 @@
   [(set_attr "type" "int2,int4")
    (set_attr "length" "2,4")])
 
+
 ;; reg == small constant comparisons are best handled by putting the result
 ;; of the comparison in a tmp reg and then using beqz/bnez.
 ;; ??? The result register doesn't contain 0/STORE_FLAG_VALUE,
@@ -1448,7 +1510,7 @@
   ""
   "*
 {
-  const char *br,*invbr;
+  char *br,*invbr;
   char asmtext[40];
 
   switch (GET_CODE (operands[1]))
@@ -1495,7 +1557,7 @@
   ""
   "*
 {
-  const char *br,*invbr;
+  char *br,*invbr;
   char asmtext[40];
 
   switch (GET_CODE (operands[1]))
@@ -1550,6 +1612,14 @@
   if (! register_operand (op1, mode))
     op1 = force_reg (mode, op1);
 
+  if (TARGET_M32RX)
+    {
+      if (! reg_or_zero_operand (op2, mode))
+        op2 = force_reg (mode, op2);
+
+      emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
+      DONE;
+    }
   if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
     {
       emit_insn (gen_seq_zero_insn (op0, op1));
@@ -1563,6 +1633,29 @@
   DONE;
 }")
 
+(define_insn "seq_insn_m32rx"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(eq:SI (match_operand:SI 1 "register_operand" "%r")
+	       (match_operand:SI 2 "reg_or_zero_operand" "rP")))
+   (clobber (reg:SI 17))]
+  "TARGET_M32RX"
+  "#"
+  [(set_attr "type" "multi")
+   (set_attr "length" "6")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(eq:SI (match_operand:SI 1 "register_operand" "")
+	       (match_operand:SI 2 "reg_or_zero_operand" "")))
+   (clobber (reg:SI 17))]
+  "TARGET_M32RX"
+  [(set (reg:SI 17)
+	(eq:SI (match_dup 1)
+	       (match_dup 2)))
+   (set (match_dup 0)
+	(reg:SI 17))]
+  "")
+
 (define_insn "seq_zero_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(eq:SI (match_operand:SI 1 "register_operand" "r")