Merge cond-optab branch.

From-SVN: r147425

4 files changed, 46 insertions, 142 deletions

diff --git a/gcc/config/m32c/cond.md b/gcc/config/m32c/cond.md
index 60d83ee..c751070 100644
--- a/gcc/config/m32c/cond.md
+++ b/gcc/config/m32c/cond.md
@@ -58,12 +58,23 @@
   [(set (reg:CC FLG_REGNO)
 	(compare (match_dup 1)
 		 (match_dup 2)))
-   (set (pc) (if_then_else (match_dup 4)
+   (set (pc) (if_then_else (match_op_dup 0 [(reg:CC FLG_REGNO) (const_int 0)])
 			   (label_ref (match_dup 3))
 			   (pc)))]
-  "operands[4] = m32c_cmp_flg_0 (operands[0]);"
+  ""
   )
 
+(define_insn "bcc_op"
+  [(set (pc)
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
+		       [(reg:CC FLG_REGNO) (const_int 0)])
+                      (label_ref (match_operand 1 ""))
+                      (pc)))]
+  ""
+  "j%c0\t%l1"
+  [(set_attr "flags" "n")]
+)
+
 (define_insn "stzx_16"
   [(set (match_operand:QI 0 "mrai_operand" "=R0w,R0w,R0w")
 	(if_then_else:QI (eq (reg:CC FLG_REGNO) (const_int 0))
@@ -113,34 +124,6 @@
   "* return m32c_output_compare(insn, operands); "
   [(set_attr "flags" "oszc")])
 
-(define_expand "cmp<mode>"
-  [(set (reg:CC FLG_REGNO)
-	(compare (match_operand:QHPSI 0 "mra_operand" "RraSd")
-		 (match_operand:QHPSI 1 "mrai_operand" "RraSdi")))]
-  ""
-  "m32c_pend_compare (operands); DONE;")
-
-(define_insn "b<code>_op"
-  [(set (pc)
-        (if_then_else (any_cond (reg:CC FLG_REGNO)
-				(const_int 0))
-                      (label_ref (match_operand 0 ""))
-                      (pc)))]
-  ""
-  "j<code>\t%l0"
-  [(set_attr "flags" "n")]
-)
-
-(define_expand "b<code>"
-  [(set (pc)
-        (if_then_else (any_cond (reg:CC FLG_REGNO)
-				(const_int 0))
-                      (label_ref (match_operand 0 ""))
-                      (pc)))]
-  ""
-  "m32c_unpend_compare ();"
-)
-
 ;; m32c_conditional_register_usage changes the setcc_gen_code array to
 ;; point to the _24 variants if needed.
 
@@ -151,51 +134,54 @@
 
 ;; These are the post-split patterns for the conditional sets.
 
-(define_insn "s<code>_op"
+(define_insn "scc_op"
   [(set (match_operand:QI 0 "register_operand" "=Rqi")
-	(any_cond:QI (reg:CC FLG_REGNO) (const_int 0)))]
+	(match_operator:QI 1 "ordered_comparison_operator"
+	 [(reg:CC FLG_REGNO) (const_int 0)]))]
   "TARGET_A16 && reload_completed"
-  "* return m32c_scc_pattern(operands, <CODE>);")
+  "* return m32c_scc_pattern(operands, GET_CODE (operands[1]));")
 
-(define_insn "s<code>_24_op"
+(define_insn "scc_24_op"
   [(set (match_operand:HI 0 "mra_operand" "=RhiSd")
-	(any_cond:HI (reg:CC FLG_REGNO) (const_int 0)))]
+	(match_operator:HI 1 "ordered_comparison_operator"
+	 [(reg:CC FLG_REGNO) (const_int 0)]))]
   "TARGET_A24 && reload_completed"
-  "sc<code>\t%0"
+  "sc%c1\t%0"
   [(set_attr "flags" "n")]
 )
 
-;; These are the pre-split patterns for the conditional sets.  Yes,
-;; there are a lot of permutations.
+;; These are the pre-split patterns for the conditional sets.
 
-(define_insn_and_split "s<code>_<mode>"
+(define_insn_and_split "cstore<mode>4"
   [(set (match_operand:QI 0 "register_operand" "=Rqi")
-	(any_cond:QI (match_operand:QHPSI 1 "mra_operand" "RraSd")
-		     (match_operand:QHPSI 2 "mrai_operand" "RraSdi")))]
+	(match_operator:QI 1 "ordered_comparison_operator"
+	 [(match_operand:QHPSI 2 "mra_operand" "RraSd")
+	  (match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
   "TARGET_A16"
   "#"
   "reload_completed"
   [(set (reg:CC FLG_REGNO)
-	(compare (match_dup 1)
-		 (match_dup 2)))
+	(compare (match_dup 2)
+		 (match_dup 3)))
    (set (match_dup 0)
-	(any_cond:QI (reg:CC FLG_REGNO) (const_int 0)))]
+	(match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]
   ""
   [(set_attr "flags" "x")]
 )
 
-(define_insn_and_split "s<code>_<mode>_24"
+(define_insn_and_split "cstore<mode>4_24"
   [(set (match_operand:HI 0 "mra_nopp_operand" "=RhiSd")
-	(any_cond:HI (match_operand:QHPSI 1 "mra_operand" "RraSd")
-		     (match_operand:QHPSI 2 "mrai_operand" "RraSdi")))]
+	(match_operator:HI 1 "ordered_comparison_operator"
+	 [(match_operand:QHPSI 2 "mra_operand" "RraSd")
+	  (match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
   "TARGET_A24"
   "#"
   "reload_completed"
   [(set (reg:CC FLG_REGNO)
-	(compare (match_dup 1)
-		 (match_dup 2)))
+	(compare (match_dup 2)
+		 (match_dup 3)))
    (set (match_dup 0)
-	(any_cond:HI (reg:CC FLG_REGNO) (const_int 0)))]
+	(match_op_dup 1 [(reg:CC FLG_REGNO) (const_int 0)]))]
   ""
   [(set_attr "flags" "x")]
 )
@@ -240,21 +226,7 @@
   [(set_attr "flags" "x")]
   )
 
-;; And these are the expanders, which read the pending compare
-;; operands to build a combined insn.
-
-(define_expand "s<code>"
-  [(set (match_operand:QI 0 "register_operand" "=Rqi")
-	(any_cond:QI (reg:CC FLG_REGNO) (const_int 0)))]
-  "TARGET_A16"
-  "m32c_expand_scc (<CODE>, operands); DONE;")
-
-(define_expand "s<code>_24"
-  [(set (match_operand:HI 0 "mra_nopp_operand" "=RhiSd")
-	(any_cond:HI (reg:CC FLG_REGNO) (const_int 0)))]
-  "TARGET_A24"
-  "m32c_expand_scc (<CODE>, operands); DONE;")
-
+;; And these are the expanders.
 
 (define_expand "movqicc"
   [(set (match_operand:QI 0 "register_operand" "")
diff --git a/gcc/config/m32c/m32c-protos.h b/gcc/config/m32c/m32c-protos.h
index 650c918..ef85727 100644
--- a/gcc/config/m32c/m32c-protos.h
+++ b/gcc/config/m32c/m32c-protos.h
@@ -45,7 +45,6 @@ void m32c_register_pragmas (void);
 int  m32c_regno_ok_for_base_p (int);
 int  m32c_trampoline_alignment (void);
 int  m32c_trampoline_size (void);
-void m32c_unpend_compare (void);
 
 #if defined(RTX_CODE) && defined(TREE_CODE)
 
@@ -58,7 +57,6 @@ rtx  m32c_function_value (const_tree, const_tree);
 
 int  m32c_cannot_change_mode_class (MM, MM, int);
 int  m32c_class_max_nregs (int, MM);
-rtx  m32c_cmp_flg_0 (rtx);
 rtx  m32c_eh_return_stackadj_rtx (void);
 void m32c_emit_eh_epilogue (rtx);
 int  m32c_expand_cmpstr (rtx *);
@@ -68,7 +66,6 @@ int  m32c_expand_movmemhi (rtx *);
 int  m32c_expand_movstr (rtx *);
 void m32c_expand_neg_mulpsi3 (rtx *);
 int  m32c_expand_setmemhi (rtx *);
-void m32c_expand_scc (int, rtx *);
 int  m32c_extra_constraint_p (rtx, char, const char *);
 int  m32c_extra_constraint_p2 (rtx, char, const char *);
 int  m32c_hard_regno_nregs (int, MM);
@@ -86,7 +83,6 @@ int  m32c_memory_move_cost (MM, int, int);
 int  m32c_modes_tieable_p (MM, MM);
 bool m32c_mov_ok (rtx *, MM);
 char * m32c_output_compare (rtx, rtx *);
-void m32c_pend_compare (rtx *);
 int  m32c_preferred_output_reload_class (rtx, int);
 int  m32c_preferred_reload_class (rtx, int);
 int  m32c_prepare_move (rtx *, MM);
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index d0980dd..17d5dd3 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -1746,22 +1746,15 @@ m32c_initialize_trampoline (rtx tramp, rtx function, rtx chainval)
 static void
 m32c_init_libfuncs (void)
 {
+  /* We do this because the M32C has an HImode operand, but the
+     M16C has an 8-bit operand.  Since gcc looks at the match data
+     and not the expanded rtl, we have to reset the optab so that
+     the right modes are found. */
   if (TARGET_A24)
     {
-      /* We do this because the M32C has an HImode operand, but the
-	 M16C has an 8-bit operand.  Since gcc looks at the match data
-	 and not the expanded rtl, we have to reset the array so that
-	 the right modes are found. */
-      setcc_gen_code[EQ] = CODE_FOR_seq_24;
-      setcc_gen_code[NE] = CODE_FOR_sne_24;
-      setcc_gen_code[GT] = CODE_FOR_sgt_24;
-      setcc_gen_code[GE] = CODE_FOR_sge_24;
-      setcc_gen_code[LT] = CODE_FOR_slt_24;
-      setcc_gen_code[LE] = CODE_FOR_sle_24;
-      setcc_gen_code[GTU] = CODE_FOR_sgtu_24;
-      setcc_gen_code[GEU] = CODE_FOR_sgeu_24;
-      setcc_gen_code[LTU] = CODE_FOR_sltu_24;
-      setcc_gen_code[LEU] = CODE_FOR_sleu_24;
+      optab_handler (cstore_optab, QImode)->insn_code = CODE_FOR_cstoreqi4_24;
+      optab_handler (cstore_optab, HImode)->insn_code = CODE_FOR_cstorehi4_24;
+      optab_handler (cstore_optab, PSImode)->insn_code = CODE_FOR_cstorepsi4_24;
     }
 }
 
@@ -3691,57 +3684,8 @@ m32c_expand_neg_mulpsi3 (rtx * operands)
   emit_insn (gen_truncsipsi2 (operands[0], temp2));
 }
 
-static rtx compare_op0, compare_op1;
-
-void
-m32c_pend_compare (rtx *operands)
-{
-  compare_op0 = operands[0];
-  compare_op1 = operands[1];
-}
-
-void
-m32c_unpend_compare (void)
-{
-  switch (GET_MODE (compare_op0))
-    {
-    case QImode:
-      emit_insn (gen_cmpqi_op (compare_op0, compare_op1));
-    case HImode:
-      emit_insn (gen_cmphi_op (compare_op0, compare_op1));
-    case PSImode:
-      emit_insn (gen_cmppsi_op (compare_op0, compare_op1));
-    default:
-      /* Just to silence the "missing case" warnings.  */ ;
-    }
-}
-
-void
-m32c_expand_scc (int code, rtx *operands)
-{
-  enum machine_mode mode = TARGET_A16 ? QImode : HImode;
-
-  emit_insn (gen_rtx_SET (mode,
-			  operands[0],
-			  gen_rtx_fmt_ee (code,
-					  mode,
-					  compare_op0,
-					  compare_op1)));
-}
-
 /* Pattern Output Functions */
 
-/* Returns a (OP (reg:CC FLG_REGNO) (const_int 0)) from some other
-   match_operand rtx's OP.  */
-rtx
-m32c_cmp_flg_0 (rtx cmp)
-{
-  return gen_rtx_fmt_ee (GET_CODE (cmp),
-			 GET_MODE (cmp),
-			 gen_rtx_REG (CCmode, FLG_REGNO),
-			 GEN_INT (0));
-}
-
 int
 m32c_expand_movcc (rtx *operands)
 {
@@ -3753,22 +3697,17 @@ m32c_expand_movcc (rtx *operands)
   if (GET_CODE (operands[2]) != CONST_INT
       || GET_CODE (operands[3]) != CONST_INT)
     return 1;
-  emit_insn (gen_cmpqi(XEXP (rel, 0), XEXP (rel, 1)));
   if (GET_CODE (rel) == NE)
     {
       rtx tmp = operands[2];
       operands[2] = operands[3];
       operands[3] = tmp;
+      rel = gen_rtx_EQ (GET_MODE (rel), XEXP (rel, 0), XEXP (rel, 1));
     }
 
-  cmp = gen_rtx_fmt_ee (GET_CODE (rel),
-			GET_MODE (rel),
-			compare_op0,
-			compare_op1);
-
   emit_move_insn (operands[0],
 		  gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
-					cmp,
+					rel,
 					operands[2],
 					operands[3]));
   return 0;
diff --git a/gcc/config/m32c/m32c.md b/gcc/config/m32c/m32c.md
index 4bc4d05..da0f8dd 100644
--- a/gcc/config/m32c/m32c.md
+++ b/gcc/config/m32c/m32c.md
@@ -60,10 +60,7 @@
 (define_mode_iterator QHSI [QI HI (SI "TARGET_A24")])
 (define_mode_attr bwl [(QI "b") (HI "w") (PSI "l") (SI "l")])
 
-(define_code_iterator any_cond [eq ne gt ge lt le gtu geu ltu leu])
 (define_code_iterator eqne_cond [eq ne])
-(define_code_iterator gl_cond [gt ge lt le gtu geu ltu leu])
-
 
 
 (define_insn "nop"