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| author | Uros Bizjak <uros@gcc.gnu.org> | 2011-04-20 21:58:23 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2011-04-20 21:58:23 +0200 |
| commit | 3b84d61f446425ee51e583b1cf1540b7a5fe636e (patch) | |
| tree | 46d79f57ef007919fad0f34cd4bd91fc42100728 /gcc/config/m32c/m32c.h | |
| parent | 8efcbecad561cde32bdefe8d08f096e6284ef928 (diff) | |
| download | gcc-3b84d61f446425ee51e583b1cf1540b7a5fe636e.zip gcc-3b84d61f446425ee51e583b1cf1540b7a5fe636e.tar.gz gcc-3b84d61f446425ee51e583b1cf1540b7a5fe636e.tar.bz2 | |
re PR target/48678 (unable to find a register to spill in class ‘GENERAL_REGS’)
PR target/48678
* config/i386/i386.md (insv): Change operand 0 constraint to
"register_operand". Change operand 1 and 2 constraint to
"const_int_operand". Expand to pinsr{b,w,d,q} * when appropriate.
* config/i386/sse.md (sse4_1_pinsrb): Export.
(sse2_pinsrw): Ditto.
(sse4_1_pinsrd): Ditto.
(sse4_1_pinsrq): Ditto.
* config/i386/i386-protos.h (ix86_expand_pinsr): Add prototype.
* config/i386/i386.c (ix86_expand_pinsr): New.
testsuite/ChangeLog:
PR target/48678
* gcc.target/i386/sse2-pinsrw.c: New test.
* gcc.target/i386/avx-vpinsrw.c: Ditto.
* gcc.target/i386/sse4_1-insvqi.c: Ditto.
* gcc.target/i386/sse2-insvhi.c: Ditto.
* gcc.target/i386/sse4_1-insvsi.c: Ditto.
* gcc.target/i386/sse4_1-insvdi.c: Ditto.
From-SVN: r172792
Diffstat (limited to 'gcc/config/m32c/m32c.h')
0 files changed, 0 insertions, 0 deletions