Add new parameter to vec_perm_const hook for specifying operand mode.

The rationale of the patch is to support vec_perm_expr of the form:
lhs = vec_perm_expr<rhs, mask>
where lhs and rhs are vector types with different lengths but have
same element type. For example, lhs is SVE vector and rhs
is corresponding AdvSIMD vector.

It would also allow to express extract even/odd and interleave operations
with a VEC_PERM_EXPR.  The interleave currently has the issue that we have
to artificially widen the inputs with "dont-care" elements.

gcc/ChangeLog:

	* target.def (vec_perm_const): Define new parameter op_mode and
	update doc.
	* doc/tm.texi: Regenerate.
	* config/aarch64/aarch64.cc (aarch64_vectorize_vec_perm_const): Adjust
	vec_perm_const hook to add new parameter op_mode and return false
	if result and operand modes do not match.
	* config/arm/arm.cc (arm_vectorize_vec_perm_const): Likewise.
	* config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Likewise.
	* config/ia64/ia64.cc (ia64_vectorize_vec_perm_const): Likewise.
	* config/mips/mips.cc (mips_vectorize_vec_perm_const): Likewise.
	* config/rs6000/rs6000.cc (rs6000_vectorize_vec_perm_const): Likewise
	* config/s390/s390.cc (s390_vectorize_vec_perm_const): Likewise.
	* config/sparc/sparc.cc (sparc_vectorize_vec_perm_const): Likewise.
	* config/i386/i386-expand.cc (ix86_vectorize_vec_perm_const): Likewise.
	* config/i386/i386-expand.h (ix86_vectorize_vec_perm_const): Adjust
	prototype.
	* config/i386/sse.md (ashrv4di3): Adjust call to vec_perm_const hook.
	(ashrv2di3): Likewise.
	* optabs.cc (expand_vec_perm_const): Likewise.
	* optabs-query.h (can_vec_perm_const_p): Adjust prototype.
	* optabs-query.cc (can_vec_perm_const_p): Define new parameter
	op_mode and pass it to vec_perm_const hook.
	(can_mult_highpart_p): Adjust call to can_vec_perm_const_p.
	* match.pd (vec_perm X Y CST): Likewise.
	* tree-ssa-forwprop.cc (simplify_vector_constructor): Likewise.
	* tree-vect-data-refs.cc (vect_grouped_store_supported): Likewise.
	(vect_grouped_load_supported): Likewise.
	(vect_shift_permute_load_chain): Likewise.
	* tree-vect-generic.cc (lower_vec_perm): Likewise.
	* tree-vect-loop-manip.cc (interleave_supported_p): Likewise.
	* tree-vect-loop.cc (have_whole_vector_shift): Likewise.
	* tree-vect-patterns.cc (vect_recog_rotate_pattern): Likewise.
	* tree-vect-slp.cc (can_duplicate_and_interleave_p): Likewise.
	(vect_transform_slp_perm_load): Likewise.
	(vectorizable_slp_permutation): Likewise.
	* tree-vect-stmts.cc (perm_mask_for_reverse): Likewise.
	(vectorizable_bswap): Likewise.
	(scan_store_can_perm_p): Likewise.
	(vect_gen_perm_mask_checked): Likewise.

1 files changed, 8 insertions, 4 deletions

diff --git a/gcc/config/ia64/ia64.cc b/gcc/config/ia64/ia64.cc
index f9fb681..25e4a47 100644
--- a/gcc/config/ia64/ia64.cc
+++ b/gcc/config/ia64/ia64.cc
@@ -332,8 +332,8 @@ static fixed_size_mode ia64_get_reg_raw_mode (int regno);
 static section * ia64_hpux_function_section (tree, enum node_frequency,
 					     bool, bool);
 
-static bool ia64_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx,
-					   const vec_perm_indices &);
+static bool ia64_vectorize_vec_perm_const (machine_mode, machine_mode, rtx,
+					   rtx, rtx, const vec_perm_indices &);
 
 static unsigned int ia64_hard_regno_nregs (unsigned int, machine_mode);
 static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode);
@@ -11751,9 +11751,13 @@ ia64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST.  */
 
 static bool
-ia64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
-			       rtx op1, const vec_perm_indices &sel)
+ia64_vectorize_vec_perm_const (machine_mode vmode, machine_mode op_mode,
+			       rtx target, rtx op0, rtx op1,
+			       const vec_perm_indices &sel)
 {
+  if (vmode != op_mode)
+    return false;
+
   struct expand_vec_perm_d d;
   unsigned char perm[MAX_VECT_LEN];
   unsigned int i, nelt, which;