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| author | Steve Ellcey <sje@cup.hp.com> | 2010-10-18 21:34:46 +0000 |
|---|---|---|
| committer | Steve Ellcey <sje@gcc.gnu.org> | 2010-10-18 21:34:46 +0000 |
| commit | 89774469f36bdee16b9c676a55cefb4724998dd5 (patch) | |
| tree | 9833f5bd49ad250fe03a924c577b832541c9f92e /gcc/config/ia64 | |
| parent | b69da3d839be206c4c1fb206b4d56cc55aba44f4 (diff) | |
| download | gcc-89774469f36bdee16b9c676a55cefb4724998dd5.zip gcc-89774469f36bdee16b9c676a55cefb4724998dd5.tar.gz gcc-89774469f36bdee16b9c676a55cefb4724998dd5.tar.bz2 | |
re PR target/36898 (Insufficient qp-mutex declarations)
2010-10-18 Steve Ellcey <sje@cup.hp.com>
PR target/36898
PR middle-end/43760
* config/ia64/ia64.c (rws_access_regno): Remove predicate check.
From-SVN: r165664
Diffstat (limited to 'gcc/config/ia64')
| -rw-r--r-- | gcc/config/ia64/ia64.c | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index f7489f9..c1135f9 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -5875,15 +5875,14 @@ rws_access_regno (int regno, struct reg_flags flags, int pred) break; case 1: - /* The register has been written via a predicate. If this is - not a complementary predicate, then we need a barrier. */ - /* ??? This assumes that P and P+1 are always complementary - predicates for P even. */ + /* The register has been written via a predicate. Treat + it like a unconditional write and do not try to check + for complementary pred reg in earlier write. */ if (flags.is_and && rws_sum[regno].written_by_and) ; else if (flags.is_or && rws_sum[regno].written_by_or) ; - else if ((rws_sum[regno].first_pred ^ 1) != pred) + else need_barrier = 1; if (!in_safe_group_barrier) rws_update (regno, flags, pred); @@ -5944,12 +5943,9 @@ rws_access_regno (int regno, struct reg_flags flags, int pred) break; case 1: - /* The register has been written via a predicate. If this is - not a complementary predicate, then we need a barrier. */ - /* ??? This assumes that P and P+1 are always complementary - predicates for P even. */ - if ((rws_sum[regno].first_pred ^ 1) != pred) - need_barrier = 1; + /* The register has been written via a predicate, assume we + need a barrier (don't check for complementary regs). */ + need_barrier = 1; break; case 2: |