md.texi (Iterators): Renamed from Macros.

	* doc/md.texi (Iterators): Renamed from Macros.  All contents
	changed to reflect rename of respectively define_code_macro and
	define_mode_macro to define_code_iterator and define_mode_iterator.
	(Mode Iterators, Code Iterators): Similar.
	* read-rtl.c (struct iterator_group, struct iterator_traverse_data)
	(uses_mode_iterator_p, apply_mode_iterator, uses_code_iterator_p)
	(apply_iterator_to_string, uses_iterator_p, apply_iterator_traverse)
	(initialize_iterators, find_iterator, check_code_iterator)
	(map_attr_string, apply_mode_maps, apply_iterator_to_rtx, add_mapping)
	(read_mapping, read_rtx_1): Similar.
	* config/alpha/sync.md, config/alpha/alpha.md, config/frv/frv.md,
	config/s390/s390.md, config/m32c/blkmov.md, config/m32c/m32c.md,
	config/spu/spu.md, config/sparc/sparc.md, config/sparc/sync.md,
	config/i386/i386.md, config/i386/mmx.md, config/i386/sse.md,
	config/i386/sync.md, config/crx/crx.md, config/xtensa/xtensa.md,
	config/cris/cris.c, config/cris/cris.md, config/ia64/sync.md,
	config/ia64/div.md, config/ia64/vect.md, config/ia64/ia64.md,
	config/m68k/m68k.md, config/rs6000/spe.md, config/rs6000/altivec.md,
	config/rs6000/sync.md, config/rs6000/rs6000.md,
	config/arm/vec-common.md, config/arm/neon.md, config/arm/iwmmxt.md,
	config/arm/arm.md, config/mips/mips-dsp.md, config/mips/mips.md,
	config/vax/vax.md, config/bfin/bfin.md: Similar.

From-SVN: r127715

4 files changed, 10 insertions, 10 deletions

diff --git a/gcc/config/ia64/div.md b/gcc/config/ia64/div.md
index d26954b..a6547a6 100644
--- a/gcc/config/ia64/div.md
+++ b/gcc/config/ia64/div.md
@@ -158,7 +158,7 @@
 ;; to be written for RFmode only and to not have to handle multiple
 ;; modes or to have to handle a register in more than one mode.
 
-(define_mode_macro SDX_F [SF DF XF])
+(define_mode_iterator SDX_F [SF DF XF])
 
 (define_insn "extend<mode>rf2"
   [(set (match_operand:RF 0 "fr_register_operand" "=f")
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 2cbec72..52f26aa 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -385,8 +385,8 @@
 }
   [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
 
-(define_mode_macro MODE [BI QI HI SI DI SF DF XF TI])
-(define_mode_macro MODE_FOR_EXTEND [QI HI SI])
+(define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
+(define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
 
 (define_mode_attr output_a [
   (BI "ld1.a %0 = %1%P1")
diff --git a/gcc/config/ia64/sync.md b/gcc/config/ia64/sync.md
index 9d99577..c467b0d 100644
--- a/gcc/config/ia64/sync.md
+++ b/gcc/config/ia64/sync.md
@@ -18,12 +18,12 @@
 ;; along with GCC; see the file COPYING3.  If not see
 ;; <http://www.gnu.org/licenses/>.
 
-(define_mode_macro IMODE [QI HI SI DI])
-(define_mode_macro I124MODE [QI HI SI])
-(define_mode_macro I48MODE [SI DI])
+(define_mode_iterator IMODE [QI HI SI DI])
+(define_mode_iterator I124MODE [QI HI SI])
+(define_mode_iterator I48MODE [SI DI])
 (define_mode_attr modesuffix [(QI "1") (HI "2") (SI "4") (DI "8")])
 
-(define_code_macro FETCHOP [plus minus ior xor and])
+(define_code_iterator FETCHOP [plus minus ior xor and])
 (define_code_attr fetchop_name
   [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
 
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index bca5d8c..994ec90 100644
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -20,9 +20,9 @@
 
 ;; Integer vector operations
 
-(define_mode_macro VECINT [V8QI V4HI V2SI])
-(define_mode_macro VECINT12 [V8QI V4HI])
-(define_mode_macro VECINT24 [V4HI V2SI])
+(define_mode_iterator VECINT [V8QI V4HI V2SI])
+(define_mode_iterator VECINT12 [V8QI V4HI])
+(define_mode_iterator VECINT24 [V4HI V2SI])
 (define_mode_attr vecsize [(V8QI "1") (V4HI "2") (V2SI "4")])
 
 (define_expand "mov<mode>"