target.h (struct gcc_target): Update prototypes of needs_block_p and gen_spec_check.

2008-10-14  Andrey Belevantsev  <abel@ispras.ru>
	    Dmitry Melnik  <dm@ispras.ru>
	    Dmitry Zhurikhin  <zhur@ispras.ru>
	    Alexander Monakov  <amonakov@ispras.ru>
	    Maxim Kuvyrkov  <maxim@codesourcery.com>

	* target.h (struct gcc_target): Update prototypes of needs_block_p
	and gen_spec_check.
	* haifa-sched.c (create_check_block_twin): Update calls to the above.
	* sel-sched.c (create_speculation_check): Likewise.
	* doc/tm.texi: Provide documentation for new target hooks.
		
	* config/ia64/ia64.c: Include sel-sched.h.  Rewrite speculation hooks.
	(ia64_gen_spec_insn): Removed.
	(get_spec_check_gen_function, insn_can_be_in_speculative_p,
	ia64_gen_spec_check): New static functions.
	(ia64_alloc_sched_context, ia64_init_sched_context, 
	ia64_set_sched_context, ia64_clear_sched_context, 
	ia64_free_sched_context, ia64_get_insn_spec_ds, 
	ia64_get_insn_checked_ds, ia64_skip_rtx_p): Declare functions.
	(ia64_needs_block_p): Change prototype.
	(ia64_gen_check): Rename to ia64_gen_spec_check.
	(ia64_adjust_cost): Rename to ia64_adjust_cost_2.  Add new parameter 
	into declaration, add special memory dependencies handling.
	(TARGET_SCHED_ALLOC_SCHED_CONTEXT, TARGET_SCHED_INIT_SCHED_CONTEXT,
	TARGET_SCHED_SET_SCHED_CONTEXT, TARGET_SCHED_CLEAR_SCHED_CONTEXT,
	TARGET_SCHED_FREE_SCHED_CONTEXT, TARGET_SCHED_GET_INSN_SPEC_DS,
	TARGET_SCHED_GET_INSN_CHECKED_DS, TARGET_SCHED_SKIP_RTX_P): 
	Define new target hooks.
	(TARGET_SCHED_GEN_CHECK): Rename to TARGET_SCHED_GEN_SPEC_CHECK.
	(ia64_optimization_options): Turn on selective scheduling with -O3, 
	disable -fauto-inc-dec. Set mflag_sched_control_spec to true by default
	with selective scheduling.
	(ia64_override_options): Initialize align_loops and align_functions 
	to 32 and 64, respectively.  Set global selective scheduling flags 
	according to target-dependent flags.
	(rtx_needs_barrier): Support UNSPEC_LDS_A.
	(group_barrier_needed): Use new mstop-bit-before-check flag. 
	Add heuristic.
	(dfa_state_size): Make global.
	(spec_check_no, max_uid): Remove.
        (mem_ops_in_group, current_cycle): New variables.
	(ia64_sched_init): Disable checks for !SCHED_GROUP_P after reload.
        Initialize new variables.
        (is_load_p, record_memory_reference): New functions.
        (ia64_dfa_sched_reorder): Lower priority of loads when limit is
        reached.
	(ia64_variable_issue): Change use of current_sched_info to 
	sched_deps_info.  Update comment.  Note if a load or a store is issued.
        (ia64_first_cycle_multipass_dfa_lookahead_guard_spec): Require a cycle
        advance if maximal number of loads or stores was issued on current 
        cycle.
	(scheduled_good_insn): New static helper function.
        (ia64_dfa_new_cycle): Assert that last_scheduled_insn is set when 
        a group barrier is needed.  Fix vertical spacing.  Guard the code
        doing state transition with last_scheduled_insn check.                
        Mark that a stop bit should be before current insn if there was a 
        cycle advance.  Update current_cycle and mem_ops_in_group.
	(ia64_h_i_d_extended): Change use of current_sched_info to
        sched_deps_info. Reallocate stops_p by larger chunks.
	(struct _ia64_sched_context): New structure.
	(ia64_sched_context_t): New typedef.
	(ia64_alloc_sched_context, ia64_init_sched_context, 
	ia64_set_sched_context, ia64_clear_sched_context,
	ia64_free_sched_context): New static functions.
	(gen_func_t): New typedef.
	(get_spec_load_gen_function): New function.
	(SPEC_GEN_EXTEND_OFFSET): Declare.	
	(ia64_set_sched_flags): Check common_sched_info instead of *flags.
	(get_mode_no_for_insn): Change the condition that prevents use of 
	special hardware registers so it can now handle pseudos.
	(get_spec_unspec_code): New function.
	(ia64_skip_rtx_p, get_insn_spec_code, ia64_get_insn_spec_ds,
	ia64_get_insn_checked_ds, ia64_gen_spec_load): New static functions.
	(ia64_speculate_insn, ia64_needs_block_p): Support branchy checks
	during selective scheduling.
	(ia64_speculate_insn): Use ds_get_speculation_types when 
	determining whether we need to change the pattern.
	(SPEC_GEN_LD_MAP, SPEC_GEN_CHECK_OFFSET): Declare.
	(ia64_spec_check_src_p): Support new speculation/check codes.
	(struct bundle_state): New field.
	(issue_nops_and_insn): Initialize it.
	(insert_bundle_state): Minimize mid-bundle stop bits.
	(important_for_bundling_p): New function.
	(get_next_important_insn): Use important_for_bundling_p.
	(bundling): When shifting TImode from unimportant insns, ignore 
	also group barriers.  Assert that best state is found before 
	the backward bundling pass.  Print number of mid-bundle stop bits.  
	Minimize mid-bundle stop bits.  Check correct calculation of 
	mid-bundle stop bits.
	(ia64_sched_finish, final_emit_insn_group_barriers): Fix formatting.
	(final_emit_insn_group_barriers): Emit stop bits before insns starting
	a new cycle.
	(sel2_run): New variable.
	(ia64_reorg): When flag_selective_scheduling2 is set, run the selective 
	scheduling pass instead of schedule_ebbs.  
	
	* config/ia64/ia64.md (speculable1, speculable2): New attributes.
	(UNSPEC_LDS_A): New UNSPEC.
	(movqi_internal, movhi_internal, movsi_internal, movdi_internal, 
	movti_internal, movsf_internal, movdf_internal, 
	movxf_internal): Make visible.  Add speculable* attributes.
	(output_c_nc): New mode attribute.
	(mov<mode>_speculative_a, zero_extend<mode>di2_speculative_a,
	mov<mode>_nc, zero_extend<mode>di2_nc, 
	advanced_load_check_nc_<mode>): New insns.
	(zero_extend*): Add speculable* attributes.

	* config/ia64/ia64.opt (msched_fp_mem_deps_zero_cost): New option.
	(msched-stop-bits-after-every-cycle): Likewise.
	(msched-max-memory-insns,
        msched-max-memory-insns-hard-limit): Likewise.
	(msched-spec-verbose): Remove.
	(msched-prefer-non-data-spec-insns,
        msched-prefer-non-control-spec-insns, msched-count-spec-in-critical-path,
	msel-sched-dont-check-control-spec): Use Target 
        Report Var instead of Common Report Var.

	* config/ia64/itanium2.md: Remove incorrect bypass.
	
	* config/ia64/t-ia64 (ia64.o): Add dependency on sel-sched.h.

Co-Authored-By: Alexander Monakov <amonakov@ispras.ru>
Co-Authored-By: Dmitry Melnik <dm@ispras.ru>
Co-Authored-By: Dmitry Zhurikhin <zhur@ispras.ru>
Co-Authored-By: Maxim Kuvyrkov <maxim@codesourcery.com>

From-SVN: r141108

1 files changed, 124 insertions, 26 deletions

diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index cf746f5..b03032d 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -82,12 +82,15 @@
    (UNSPEC_VECT_EXTR		31)
    (UNSPEC_LDA                  40)
    (UNSPEC_LDS                  41)
-   (UNSPEC_LDSA                 42)
-   (UNSPEC_LDCCLR               43)
-   (UNSPEC_CHKACLR              45)
-   (UNSPEC_CHKS                 47)	
-   (UNSPEC_FR_RECIP_APPROX_RES  48)
-   (UNSPEC_FR_SQRT_RECIP_APPROX_RES 49)
+   (UNSPEC_LDS_A                42)
+   (UNSPEC_LDSA                 43)
+   (UNSPEC_LDCCLR               44)
+   (UNSPEC_LDCNC                45)
+   (UNSPEC_CHKACLR              46)
+   (UNSPEC_CHKANC               47)
+   (UNSPEC_CHKS                 48)
+   (UNSPEC_FR_RECIP_APPROX_RES  49)
+   (UNSPEC_FR_SQRT_RECIP_APPROX_RES 50)
   ])
 
 (define_constants
@@ -185,6 +188,10 @@
 (define_attr "control_speculative" "no,yes" (const_string "no"))
 
 (define_attr "check_load" "no,yes" (const_string "no"))
+
+(define_attr "speculable1" "no,yes" (const_string "no"))
+
+(define_attr "speculable2" "no,yes" (const_string "no"))
 
 ;; DFA descriptions of ia64 processors used for insn scheduling and
 ;; bundling.
@@ -234,7 +241,9 @@
    ld1%O1 %0 = %1%P1
    st1%Q0 %0 = %1%P0
    mov %0 = %1"
-  [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")])
+  [(set_attr "itanium_class" "icmp,icmp,unknown,unknown,tbit,ialu,ld,st,ialu")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,  no,  no,     no,     no,  no, yes,no,no")])
 
 (define_split
   [(set (match_operand:BI 0 "register_operand" "")
@@ -273,7 +282,7 @@
   operands[1] = op1;
 })
 
-(define_insn "*movqi_internal"
+(define_insn "movqi_internal"
   [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
 	(match_operand:QI 1 "move_operand"        "rO,J,m,rO,*f,rO,*f"))]
   "ia64_move_ok (operands[0], operands[1])"
@@ -285,7 +294,9 @@
    getf.sig %0 = %1
    setf.sig %0 = %r1
    mov %0 = %1"
-  [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
+  [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,  no, yes,no,no,  no,  no")])
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "general_operand" "")
@@ -298,7 +309,7 @@
   operands[1] = op1;
 })
 
-(define_insn "*movhi_internal"
+(define_insn "movhi_internal"
   [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
 	(match_operand:HI 1 "move_operand"        "rO,J,m,rO,*f,rO,*f"))]
   "ia64_move_ok (operands[0], operands[1])"
@@ -310,7 +321,9 @@
    getf.sig %0 = %1
    setf.sig %0 = %r1
    mov %0 = %1"
-  [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")])
+  [(set_attr "itanium_class" "ialu,ialu,ld,st,frfr,tofr,fmisc")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,  no, yes,no,no,  no,  no")])
 
 (define_expand "movsi"
   [(set (match_operand:SI 0 "general_operand" "")
@@ -323,7 +336,7 @@
   operands[1] = op1;
 })
 
-(define_insn "*movsi_internal"
+(define_insn "movsi_internal"
   [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r,r, m, r,*f,*f, r,*d")
 	(match_operand:SI 1 "move_operand"        "rO,J,j,i,m,rO,*f,rO,*f,*d,rK"))]
   "ia64_move_ok (operands[0], operands[1])"
@@ -340,7 +353,9 @@
   mov %0 = %1
   mov %0 = %r1"
   ;; frar_m, toar_m ??? why not frar_i and toar_i
-  [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
+  [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,  no,  no,  no,   yes,no,no,  no,  no,   no,    no")])
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "general_operand" "")
@@ -353,7 +368,7 @@
   operands[1] = op1;
 })
 
-(define_insn "*movdi_internal"
+(define_insn "movdi_internal"
   [(set (match_operand:DI 0 "destination_operand"
 		    "=r,r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
 	(match_operand:DI 1 "move_operand"
@@ -387,7 +402,9 @@
 
   return alt[which_alternative];
 }
-  [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
+  [(set_attr "itanium_class" "ialu,ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,  no,  no,  no,   yes,no,no,  no,  no,   yes,no, no,  no,  no,    no,    no,    no,    no,  no")])
 
 (define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
 (define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
@@ -472,6 +489,26 @@
   (XF "ldfe.c.clr %0 = %1%P1")
   (TI "ldfp8.c.clr %X0 = %1%P1")])
 
+(define_mode_attr output_c_nc [
+  (BI "ld1.c.nc%O1 %0 = %1%P1")
+  (QI "ld1.c.nc%O1 %0 = %1%P1")
+  (HI "ld2.c.nc%O1 %0 = %1%P1")
+  (SI "ld4.c.nc%O1 %0 = %1%P1")
+  (DI
+   "@
+    ld8.c.nc%O1 %0 = %1%P1
+    ldf8.c.nc %0 = %1%P1")
+  (SF
+   "@
+    ldfs.c.nc %0 = %1%P1
+    ld4.c.nc%O1 %0 = %1%P1")
+  (DF
+   "@
+    ldfd.c.nc %0 = %1%P1
+    ld8.c.nc%O1 %0 = %1%P1")
+  (XF "ldfe.c.nc %0 = %1%P1")
+  (TI "ldfp8.c.nc %X0 = %1%P1")])
+
 (define_mode_attr ld_reg_constr [(BI "=*r") (QI "=r") (HI "=r") (SI "=r") (DI "=r,*f") (SF "=f,*r") (DF "=f,*r") (XF "=f") (TI "=*x")])
 (define_mode_attr ldc_reg_constr [(BI "+*r") (QI "+r") (HI "+r") (SI "+r") (DI "+r,*f") (SF "+f,*r") (DF "+f,*r") (XF "+f") (TI "+*x")])
 (define_mode_attr chk_reg_constr [(BI "*r") (QI "r") (HI "r") (SI "r") (DI "r,*f") (SF "f,*r") (DF "f,*r") (XF "f") (TI "*x")])
@@ -530,6 +567,15 @@
    (set_attr "data_speculative" "<attr_yes>")
    (set_attr "control_speculative" "<attr_yes>")])
 
+(define_insn "mov<mode>_speculative_a"
+  [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ld_reg_constr>")
+	(unspec:MODE [(match_operand:MODE 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A))]
+  "ia64_move_ok (operands[0], operands[1])"
+  "<output_sa>"
+  [(set_attr "itanium_class" "<ld_class>")
+   (set_attr "data_speculative" "<attr_yes>")
+   (set_attr "control_speculative" "<attr_yes>")])
+
 (define_insn "zero_extend<mode>di2_speculative_advanced"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
 	(zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDSA)))]
@@ -539,6 +585,15 @@
    (set_attr "data_speculative" "<attr_yes>")
    (set_attr "control_speculative" "<attr_yes>")])
 
+(define_insn "zero_extend<mode>di2_speculative_a"
+  [(set (match_operand:DI 0 "gr_register_operand" "=r")
+	(zero_extend:DI (unspec:MODE_FOR_EXTEND [(match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>")] UNSPEC_LDS_A)))]
+  ""
+  "<output_sa>"
+  [(set_attr "itanium_class" "<ld_class>")
+   (set_attr "data_speculative" "<attr_yes>")
+   (set_attr "control_speculative" "<attr_yes>")])
+
 (define_insn "mov<mode>_clr"
   [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
 	(if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
@@ -549,6 +604,16 @@
   [(set_attr "itanium_class" "<ld_class>")
    (set_attr "check_load" "<attr_yes>")])
 
+(define_insn "mov<mode>_nc"
+  [(set (match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<ldc_reg_constr>")
+	(if_then_else:MODE (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
+			   (match_operand:MODE 1 "memory_operand" "<mem_constr>")
+			   (match_dup 0)))]
+  "ia64_move_ok (operands[0], operands[1])"
+  "<output_c_nc>"
+  [(set_attr "itanium_class" "<ld_class>")
+   (set_attr "check_load" "<attr_yes>")])
+
 (define_insn "zero_extend<mode>di2_clr"
   [(set (match_operand:DI 0 "gr_register_operand" "+r")
 	(if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCCLR) (const_int 0))
@@ -559,6 +624,16 @@
   [(set_attr "itanium_class" "<ld_class>")
    (set_attr "check_load" "<attr_yes>")])
 
+(define_insn "zero_extend<mode>di2_nc"
+  [(set (match_operand:DI 0 "gr_register_operand" "+r")
+	(if_then_else:DI (ne (unspec [(match_dup 0)] UNSPEC_LDCNC) (const_int 0))
+			 (zero_extend:DI (match_operand:MODE_FOR_EXTEND 1 "memory_operand" "<mem_constr>"))
+			 (match_dup 0)))]
+  ""
+  "<output_c_nc>"
+  [(set_attr "itanium_class" "<ld_class>")
+   (set_attr "check_load" "<attr_yes>")])
+
 (define_insn "advanced_load_check_clr_<mode>"
   [(set (pc)
         (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKACLR) (const_int 0))
@@ -568,6 +643,15 @@
   "chk.a.clr %0, %l1"
   [(set_attr "itanium_class" "<chka_class>")])
 
+(define_insn "advanced_load_check_nc_<mode>"
+  [(set (pc)
+        (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKANC) (const_int 0))
+                      (pc)
+                      (label_ref (match_operand 1 "" ""))))]
+  ""
+  "chk.a.clr %0, %l1"
+  [(set_attr "itanium_class" "<chka_class>")])
+
 (define_insn "speculation_check_<mode>"
   [(set (pc) 
         (if_then_else (ne (unspec [(match_operand:MODE 0 "<reg_pred_prefix>_register_operand" "<chk_reg_constr>")] UNSPEC_CHKS) (const_int 0))
@@ -863,7 +947,7 @@
   operands[1] = op1;
 })
 
-(define_insn_and_split "*movti_internal"
+(define_insn_and_split "movti_internal"
   [(set (match_operand:TI 0 "destination_operand" "=r,   *fm,*x,*f,  Q")
 	(match_operand:TI 1 "general_operand"     "r*fim,r,  Q, *fOQ,*f"))]
   "ia64_move_ok (operands[0], operands[1])"
@@ -879,7 +963,9 @@
   ia64_split_tmode_move (operands);
   DONE;
 }
-  [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")])
+  [(set_attr "itanium_class" "unknown,unknown,fldp,unknown,unknown")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,     no,     yes, no,     no")])
 
 ;; Floating Point Moves
 ;;
@@ -897,7 +983,7 @@
   operands[1] = op1;
 })
 
-(define_insn "*movsf_internal"
+(define_insn "movsf_internal"
   [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
 	(match_operand:SF 1 "general_operand"     "fG,Q,fG,fG,*r,*r, m,*r"))]
   "ia64_move_ok (operands[0], operands[1])"
@@ -910,7 +996,9 @@
    mov %0 = %1
    ld4%O1 %0 = %1%P1
    st4%Q0 %0 = %1%P0"
-  [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
+  [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,   yes,no, no,  no,  no, yes,no")])
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "general_operand" "")
@@ -923,7 +1011,7 @@
   operands[1] = op1;
 })
 
-(define_insn "*movdf_internal"
+(define_insn "movdf_internal"
   [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
 	(match_operand:DF 1 "general_operand"     "fG,Q,fG,fG,*r,*r, m,*r"))]
   "ia64_move_ok (operands[0], operands[1])"
@@ -936,7 +1024,9 @@
    mov %0 = %1
    ld8%O1 %0 = %1%P1
    st8%Q0 %0 = %1%P0"
-  [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
+  [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,   yes,no, no,  no,  no, yes,no")])
 
 ;; With no offsettable memory references, we've got to have a scratch
 ;; around to play with the second word if the variable winds up in GRs.
@@ -951,7 +1041,7 @@
 
 ;; ??? There's no easy way to mind volatile acquire/release semantics.
 
-(define_insn "*movxf_internal"
+(define_insn "movxf_internal"
   [(set (match_operand:XF 0 "destination_operand" "=f,f, m")
 	(match_operand:XF 1 "general_operand"     "fG,m,fG"))]
   "ia64_move_ok (operands[0], operands[1])"
@@ -959,7 +1049,9 @@
    mov %0 = %F1
    ldfe %0 = %1%P1
    stfe %0 = %F1%P0"
-  [(set_attr "itanium_class" "fmisc,fld,stf")])
+  [(set_attr "itanium_class" "fmisc,fld,stf")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no,   yes,no")])
 
 ;; Same as for movxf, but for RFmode.
 (define_expand "movrf"
@@ -1049,7 +1141,9 @@
   "@
    zxt1 %0 = %1
    ld1%O1 %0 = %1%P1"
-  [(set_attr "itanium_class" "xtd,ld")])
+  [(set_attr "itanium_class" "xtd,ld")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no, yes")])
 
 (define_insn "zero_extendhidi2"
   [(set (match_operand:DI 0 "gr_register_operand" "=r,r")
@@ -1058,7 +1152,9 @@
   "@
    zxt2 %0 = %1
    ld2%O1 %0 = %1%P1"
-  [(set_attr "itanium_class" "xtd,ld")])
+  [(set_attr "itanium_class" "xtd,ld")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no, yes")])
 
 (define_insn "zero_extendsidi2"
   [(set (match_operand:DI 0 "grfr_register_operand" "=r,r,?f")
@@ -1069,7 +1165,9 @@
    addp4 %0 = %1, r0
    ld4%O1 %0 = %1%P1
    fmix.r %0 = f0, %1"
-  [(set_attr "itanium_class" "ialu,ld,fmisc")])
+  [(set_attr "itanium_class" "ialu,ld,fmisc")
+   (set_attr "speculable1"   "yes")
+   (set_attr "speculable2"   "no, yes,no")])
 
 ;; Convert between floating point types of different sizes.