haifa-sched.c: Convert to target hooks.

	* haifa-sched.c: Convert to target hooks.  Macros replaced
	are ISSUE_RATE, ADJUST_COST, ADJUST_PRIORITY, MD_SCHED_INIT,
	MD_SCHED_REORDER, MD_SCHED_REORDER2, MD_SCHED_VARIABLE_ISSUE,
	MD_SCHED_FINISH, and HAVE_cycle_display.
	* target-def.h (TARGET_SCHED_ADJUST_COST,
	TARGET_SCHED_ADJUST_PRIORITY, TARGET_SCHED_ISSUE_RATE,
	TARGET_SCHED_VARIABLE_ISSUE, TARGET_SCHED_INIT,
	TARGET_SCHED_FINISH, TARGET_SCHED_REORDER,
	TARGET_SCHED_REORDER2, TARGET_SCHED_CYCLE_DISPLAY):
	New hook #defines to be overridden.
	(TARGET_SCHED): Bring them all together.
	(TARGET_INITIALIZER): Update.
	* target.h: Don't forward declare struct rtx_def.  Use 'rtx'
	instead of 'struct rtx_def *' throughout.
	(struct sched): New set of hooks for the scheduler.
	* Makefile.in (haifa-sched.o): Depend on target.h.
	* doc/tm.texi: Document the new scheduler hooks, together in
	their own section, instead of scattered around.
	Fix a bunch of underfull/overfull hboxes.

	* a29k.h, alpha.h, arm.h, c4x.h, convex.h, d30v.h, i386.h,
	ia64.h, m32r.h, m88k.h, mips.h, pa.h, rs6000.h, s390.h, sh.h,
	sparc.h: Don't define any of the old scheduler macros.

	* a29k.c, alpha.c, arm.c, c4x.c, convex.c, d30v.c, i386.c,
	ia64.c, m32r.c, m88k.c, mips.c, pa.c, rs6000.c, s390.c, sh.c,
	sparc.c: Create hook functions from code extracted from
	corresponding target header, or make existing hooks static, as
	appropriate.  Set the appropriate entries in targetm.

	* alpha-protos.h, arm-protos.h, c4x-protos.h, d30v-protos.h,
	i386-protos.h, ia64-protos.h, m32r-protos.h, pa-protos.h,
	rs6000-protos.h, s390-protos.h, sparc-protos.h:
	Remove prototypes for functions which are now static.

	* d30v.h, d30v.c, m32r.h, m32r.c: Remove #ifdef HAIFA and
	related gunk; the Haifa scheduler is now the only choice.

From-SVN: r45009

1 files changed, 60 insertions, 10 deletions

diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index d7474ac..360e2b3 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -141,6 +141,18 @@ static int ia64_valid_type_attribute PARAMS((tree, tree, tree, tree));
 static void ia64_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
 static void ia64_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
 static void ia64_output_function_end_prologue PARAMS ((FILE *));
+
+static int ia64_issue_rate PARAMS ((void));
+static int ia64_adjust_cost PARAMS ((rtx, rtx, rtx, int));
+static void ia64_sched_init PARAMS ((FILE *, int, int));
+static void ia64_sched_finish PARAMS ((FILE *, int));
+static int ia64_internal_sched_reorder PARAMS ((FILE *, int, rtx *,
+						int *, int, int));
+static int ia64_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
+static int ia64_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
+static int ia64_variable_issue PARAMS ((FILE *, int, rtx, int));
+static rtx ia64_cycle_display PARAMS ((int, rtx));
+
 
 /* Initialize the GCC target structure.  */
 #undef TARGET_VALID_TYPE_ATTRIBUTE
@@ -159,6 +171,23 @@ static void ia64_output_function_end_prologue PARAMS ((FILE *));
 #undef TARGET_ASM_FUNCTION_EPILOGUE
 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
 
+#undef TARGET_SCHED_ADJUST_COST
+#define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
+#undef TARGET_SCHED_ISSUE_RATE
+#define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
+#undef TARGET_SCHED_VARIABLE_ISSUE
+#define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
+#undef TARGET_SCHED_INIT
+#define TARGET_SCHED_INIT ia64_sched_init
+#undef TARGET_SCHED_FINISH
+#define TARGET_SCHED_FINISH ia64_sched_finish
+#undef TARGET_SCHED_REORDER
+#define TARGET_SCHED_REORDER ia64_sched_reorder
+#undef TARGET_SCHED_REORDER2
+#define TARGET_SCHED_REORDER2 ia64_sched_reorder2
+#undef TARGET_SCHED_CYCLE_DISPLAY
+#define TARGET_SCHED_CYCLE_DISPLAY ia64_cycle_display
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 /* Return 1 if OP is a valid operand for the MEM of a CALL insn.  */
@@ -5064,7 +5093,7 @@ itanium_split_issue (p, begin)
 
 /* Return the maximum number of instructions a cpu can issue.  */
 
-int
+static int
 ia64_issue_rate ()
 {
   return 6;
@@ -5087,7 +5116,7 @@ ia64_single_set (insn)
 /* Adjust the cost of a scheduling dependency.  Return the new cost of
    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
 
-int
+static int
 ia64_adjust_cost (insn, link, dep_insn, cost)
      rtx insn, link, dep_insn;
      int cost;
@@ -5465,7 +5494,7 @@ rotate_two_bundles (dump)
 
 /* We're beginning a new block.  Initialize data structures as necessary.  */
 
-void
+static void
 ia64_sched_init (dump, sched_verbose, max_ready)
      FILE *dump ATTRIBUTE_UNUSED;
      int sched_verbose ATTRIBUTE_UNUSED;
@@ -5987,8 +6016,8 @@ nop_cycles_until (clock_var, dump)
 /* We are about to being issuing insns for this clock cycle.
    Override the default sort algorithm to better slot instructions.  */
 
-int
-ia64_sched_reorder (dump, sched_verbose, ready, pn_ready,
+static int
+ia64_internal_sched_reorder (dump, sched_verbose, ready, pn_ready,
 		    reorder_type, clock_var)
      FILE *dump ATTRIBUTE_UNUSED;
      int sched_verbose ATTRIBUTE_UNUSED;
@@ -6139,10 +6168,22 @@ ia64_sched_reorder (dump, sched_verbose, ready, pn_ready,
 			  ready, e_ready, reorder_type == 1);
 }
 
+static int
+ia64_sched_reorder (dump, sched_verbose, ready, pn_ready, clock_var)
+     FILE *dump;
+     int sched_verbose;
+     rtx *ready;
+     int *pn_ready;
+     int clock_var;
+{
+  return ia64_internal_sched_reorder (dump, sched_verbose, ready,
+				      pn_ready, 0, clock_var);
+}
+
 /* Like ia64_sched_reorder, but called after issuing each insn.
    Override the default sort algorithm to better slot instructions.  */
 
-int
+static int
 ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
      FILE *dump ATTRIBUTE_UNUSED;
      int sched_verbose ATTRIBUTE_UNUSED;
@@ -6232,8 +6273,9 @@ ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
 
   if (*pn_ready > 0)
     {
-      int more = ia64_sched_reorder (dump, sched_verbose, ready, pn_ready, 1,
-				     clock_var);
+      int more = ia64_internal_sched_reorder (dump, sched_verbose,
+					      ready, pn_ready, 1,
+					      clock_var);
       if (more)
 	return more;
       /* Did we schedule a stop?  If so, finish this cycle.  */
@@ -6253,7 +6295,7 @@ ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
 /* We are about to issue INSN.  Return the number of insns left on the
    ready queue that can be issued this cycle.  */
 
-int
+static int
 ia64_variable_issue (dump, sched_verbose, insn, can_issue_more)
      FILE *dump;
      int sched_verbose;
@@ -6315,7 +6357,7 @@ ia64_variable_issue (dump, sched_verbose, insn, can_issue_more)
 
 /* Free data allocated by ia64_sched_init.  */
 
-void
+static void
 ia64_sched_finish (dump, sched_verbose)
      FILE *dump;
      int sched_verbose;
@@ -6326,6 +6368,14 @@ ia64_sched_finish (dump, sched_verbose)
   free (sched_types);
   free (sched_ready);
 }
+
+static rtx
+ia64_cycle_display (clock, last)
+     int clock;
+     rtx last;
+{
+  return emit_insn_after (gen_cycle_display (GEN_INT (clock)), last);
+}
 
 /* Emit pseudo-ops for the assembler to describe predicate relations.
    At present this assumes that we only consider predicate pairs to