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authorJim Wilson <wilson@cygnus.com>1998-05-14 13:00:18 +0000
committerJim Wilson <wilson@gcc.gnu.org>1998-05-14 06:00:18 -0700
commit2129b0816f369ee6bf172e7065b0de137ac9c7f7 (patch)
tree46357ccaac87478f11cb51b84425f5e44399f316 /gcc/config/i960/i960.c
parentf2ee215beb3e13681e952395335f30dec161876a (diff)
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Patch from Gary McGary to fix i960 problem with out-of-range shifts.
* i960.h (hard_regno_mode_ok): Changed to function from array of unsigned. (HARD_REGNO_MODE_OK): Call function instead of testing bit. * i960.c (hard_regno_mode_ok): Changed to function from array of unsigned. From-SVN: r19745
Diffstat (limited to 'gcc/config/i960/i960.c')
-rw-r--r--gcc/config/i960/i960.c71
1 files changed, 44 insertions, 27 deletions
diff --git a/gcc/config/i960/i960.c b/gcc/config/i960/i960.c
index 11b2a21..f87b02c 100644
--- a/gcc/config/i960/i960.c
+++ b/gcc/config/i960/i960.c
@@ -2067,40 +2067,57 @@ i960_alignment (size, align)
}
#endif
-/* Modes for condition codes. */
-#define C_MODES \
- ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
-/* Modes for single-word (and smaller) quantities. */
-#define S_MODES \
- (~C_MODES \
- & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
- | (1 << (int) DFmode) | (1 << (int) XFmode)))
-
-/* Modes for double-word (and smaller) quantities. */
-#define D_MODES \
- (~C_MODES \
- & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
+int
+hard_regno_mode_ok (regno, mode)
+ int regno;
+ enum machine_mode mode;
+{
+ if (regno < 32)
+ {
+ switch (mode)
+ {
+ case CCmode: case CC_UNSmode: case CC_CHKmode:
+ return 0;
-/* Modes for quad-word quantities. */
-#define T_MODES (~C_MODES)
+ case DImode: case DFmode:
+ return (regno & 1) == 0;
-/* Modes for single-float quantities. */
-#define SF_MODES ((1 << (int) SFmode))
+ case TImode: case XFmode:
+ return (regno & 3) == 0;
-/* Modes for double-float quantities. */
-#define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
+ default:
+ return 1;
+ }
+ }
+ else if (regno >= 32 && regno < 36)
+ {
+ switch (mode)
+ {
+ case SFmode: case DFmode: case XFmode:
+ case SCmode: case DCmode:
+ return 1;
-/* Modes for quad-float quantities. */
-#define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
+ default:
+ return 0;
+ }
+ }
+ else if (regno == 36)
+ {
+ switch (mode)
+ {
+ case CCmode: case CC_UNSmode: case CC_CHKmode:
+ return 1;
-unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
- T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
- T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
- T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
- T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
+ default:
+ return 0;
+ }
+ }
+ else if (regno == 37)
+ return 0;
- XF_MODES, XF_MODES, XF_MODES, XF_MODES, C_MODES};
+ abort ();
+}
/* Return the minimum alignment of an expression rtx X in bytes. This takes