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| author | Uros Bizjak <ubizjak@gmail.com> | 2017-04-02 20:19:02 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2017-04-02 20:19:02 +0200 |
| commit | d4a8fcafe5d9a239eca55b5cc9ac6460438f0809 (patch) | |
| tree | bebcdfb8401a4d13f86b1f174b1fa80ab8e9134f /gcc/config/i386 | |
| parent | 5738fe8899ffc59fddc32dc05068785f5e74dc5e (diff) | |
| download | gcc-d4a8fcafe5d9a239eca55b5cc9ac6460438f0809.zip gcc-d4a8fcafe5d9a239eca55b5cc9ac6460438f0809.tar.gz gcc-d4a8fcafe5d9a239eca55b5cc9ac6460438f0809.tar.bz2 | |
re PR target/80250 (ICE in in final_scan_insn, at final.c:3025 for __builtin_ia32_vp4dpwssds_mask builtin)
PR target/80250
* config/i386/sse.md (mov<IMOD4:mode>): Remove insn pattern.
(mov<IMOD4:mode>): New expander.
(*mov<IMOD4:mode>_internal): New insn and split pattern.
From-SVN: r246637
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/sse.md | 44 |
1 files changed, 29 insertions, 15 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0ea06c5..817762c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -19707,24 +19707,38 @@ (define_mode_attr imod4_narrow [(V64SF "V16SF") (V64SI "V16SI")]) -(define_insn "mov<mode>" +(define_expand "mov<mode>" [(set (match_operand:IMOD4 0 "nonimmediate_operand") - (match_operand:IMOD4 1 "general_operand"))] + (match_operand:IMOD4 1 "vector_move_operand"))] "TARGET_AVX512F" - "#") +{ + ix86_expand_vector_move (<MODE>mode, operands); + DONE; +}) -(define_split - [(set (match_operand:IMOD4 0 "register_operand") - (match_operand:IMOD4 1 "nonimmediate_operand"))] - "TARGET_AVX512F && reload_completed" - [(set (subreg:<imod4_narrow> (match_dup 0) 0) - (subreg:<imod4_narrow> (match_dup 1) 0)) - (set (subreg:<imod4_narrow> (match_dup 0) 64) - (subreg:<imod4_narrow> (match_dup 1) 64)) - (set (subreg:<imod4_narrow> (match_dup 0) 128) - (subreg:<imod4_narrow> (match_dup 1) 128)) - (set (subreg:<imod4_narrow> (match_dup 0) 192) - (subreg:<imod4_narrow> (match_dup 1) 192))]) +(define_insn_and_split "*mov<mode>_internal" + [(set (match_operand:IMOD4 0 "nonimmediate_operand" "=v,v ,m") + (match_operand:IMOD4 1 "vector_move_operand" " C,vm,v"))] + "TARGET_AVX512F + && (register_operand (operands[0], <MODE>mode) + || register_operand (operands[1], <MODE>mode))" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx op0, op1; + int i; + + for (i = 0; i < 4; i++) + { + op0 = simplify_subreg + (<imod4_narrow>mode, operands[0], <MODE>mode, i * 64); + op1 = simplify_subreg + (<imod4_narrow>mode, operands[1], <MODE>mode, i * 64); + emit_move_insn (op0, op1); + } + DONE; +}) (define_insn "avx5124fmaddps_4fmaddps" [(set (match_operand:V16SF 0 "register_operand" "=v") |