sse.md (*sse_concatv4sf): Renamed to ...

gcc/

2008-05-12  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/sse.md (*sse_concatv4sf): Renamed to ...
	(*vec_concatv4sf_sse): This.
	(*sse2_concatv2si): Renamed to ...
	(*vec_concatv2si_sse2): This.
	(*sse1_concatv2si): Renamed to ...
	(*vec_concatv2si_sse): This.
	(*vec_concatv2di_rex): Renamed to ...
	(*vec_concatv2di_rex64): This.
	(*vec_concatv2si_sse4_1): New.
	(*vec_concatv2di_rex64_sse4_1): Likewise.

gcc/testsuite

2008-05-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gcc.target/i386/sse2-set-epi32-1.c: New.
	* gcc.target/i386/sse2-set-epi64x-1.c: Likewise.
	* gcc.target/i386/sse4_1-set-epi32-1.c: Likewise.
	* gcc.target/i386/sse4_1-set-epi64x-1.c: Likewise.

From-SVN: r135229

1 files changed, 29 insertions, 5 deletions

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index d31aceb..983ffcf 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2253,7 +2253,7 @@
 ;; ??? In theory we can match memory for the MMX alternative, but allowing
 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
 ;; alternatives pretty much forces the MMX alternative to be chosen.
-(define_insn "*sse_concatv2sf"
+(define_insn "*vec_concatv2sf_sse"
   [(set (match_operand:V2SF 0 "register_operand"     "=x,x,*y,*y")
 	(vec_concat:V2SF
 	  (match_operand:SF 1 "nonimmediate_operand" " 0,m, 0, m")
@@ -2267,7 +2267,7 @@
   [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
    (set_attr "mode" "V4SF,SF,DI,DI")])
 
-(define_insn "*sse_concatv4sf"
+(define_insn "*vec_concatv4sf_sse"
   [(set (match_operand:V4SF 0 "register_operand"   "=x,x")
 	(vec_concat:V4SF
 	  (match_operand:V2SF 1 "register_operand" " 0,0")
@@ -4726,10 +4726,22 @@
   [(set_attr "type" "sselog1,ssemov")
    (set_attr "mode" "TI,V4SF")])
 
+(define_insn "*vec_concatv2si_sse4_1"
+  [(set (match_operand:V2SI 0 "register_operand" "=x,x")
+	(vec_concat:V2SI
+	  (match_operand:SI 1 "nonimmediate_operand" "0,rm")
+	  (match_operand:SI 2 "nonimmediate_operand" "rm,0")))]
+  "TARGET_SSE4_1"
+  "@
+  pinsrd\t{$0x1, %2, %0|%0, %2, 0x1}
+  pinsrd\t{$0x0, %2, %0|%0, %2, 0x0}"
+  [(set_attr "type" "sselog")
+   (set_attr "mode" "TI")])
+
 ;; ??? In theory we can match memory for the MMX alternative, but allowing
 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
 ;; alternatives pretty much forces the MMX alternative to be chosen.
-(define_insn "*sse2_concatv2si"
+(define_insn "*vec_concatv2si_sse2"
   [(set (match_operand:V2SI 0 "register_operand"     "=Y2, Y2,*y,*y")
 	(vec_concat:V2SI
 	  (match_operand:SI 1 "nonimmediate_operand" " 0 ,rm , 0,rm")
@@ -4743,7 +4755,7 @@
   [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
    (set_attr "mode" "TI,TI,DI,DI")])
 
-(define_insn "*sse1_concatv2si"
+(define_insn "*vec_concatv2si_sse"
   [(set (match_operand:V2SI 0 "register_operand"     "=x,x,*y,*y")
 	(vec_concat:V2SI
 	  (match_operand:SI 1 "nonimmediate_operand" " 0,m, 0,*rm")
@@ -4770,6 +4782,18 @@
   [(set_attr "type" "sselog,ssemov,ssemov")
    (set_attr "mode" "TI,V4SF,V2SF")])
 
+(define_insn "*vec_concatv2di_rex64_sse4_1"
+  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
+	(vec_concat:V2DI
+	  (match_operand:DI 1 "nonimmediate_operand" "0,rm")
+	  (match_operand:DI 2 "nonimmediate_operand" "rm,0")))]
+  "TARGET_64BIT && TARGET_SSE4_1"
+  "@
+  pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
+  pinsrq\t{$0x0, %2, %0|%0, %2, 0x0}"
+  [(set_attr "type" "sselog")
+   (set_attr "mode" "TI")])
+
 (define_insn "vec_concatv2di"
   [(set (match_operand:V2DI 0 "register_operand"     "=Y2,?Y2,Y2,x,x,x")
 	(vec_concat:V2DI
@@ -4786,7 +4810,7 @@
   [(set_attr "type" "ssemov,ssemov,sselog,ssemov,ssemov,ssemov")
    (set_attr "mode" "TI,TI,TI,V4SF,V2SF,V2SF")])
 
-(define_insn "*vec_concatv2di_rex"
+(define_insn "*vec_concatv2di_rex64"
   [(set (match_operand:V2DI 0 "register_operand"     "=Y2,Yi,!Y2,Y2,x,x,x")
 	(vec_concat:V2DI
 	  (match_operand:DI 1 "nonimmediate_operand" "  m,r ,*y ,0 ,0,0,m")