optabs.h (enum optab_index): Add new OTI_exp10 and OTI_exp2.

2004-03-10  Uros Bizjak  <uros@kss-loka.si>

	* optabs.h (enum optab_index): Add new OTI_exp10 and OTI_exp2.
	(exp10_optab, exp2_optab): Define corresponding macros.
	* optabs.c (init_optabs): Initialize exp10_optab and exp2_optab.
	* genopinit.c (optabs): Implement exp10_optab and exp2_optab
	using exp10?f2 and exp2?f2 patterns.
	* builtins.c (expand_builtin_mathfn): Handle BUILT_IN_EXP10{,F,L}
	using exp10_optab, and BUILT_IN_EXP2{,F,L} using exp2_optab.
	(expand_builtin): Expand BUILT_IN_EXP10{,F,L} and BUILT_IN_EXP2{,F,L}
	using expand_builtin_mathfn if flag_unsafe_math_optimizations is set.

	* config/i386/i386.md (exp10sf2, exp10df2, exp10xf2, exp2sf2,
	exp2df2, exp2xf2): New patterns to implement exp10, exp10f, exp10l,
	exp2, exp2f and exp2l built-ins as inline x87 intrinsics.

	* gcc.dg/builtins-34.c: New test.

From-SVN: r79279

1 files changed, 131 insertions, 0 deletions

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 2bee357..c9e7c8c 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -15268,6 +15268,7 @@
    (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
    (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
    (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
+
    (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
    (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
    (parallel [(set (match_operand:DF 0 "register_operand" "")
@@ -15309,6 +15310,136 @@
   emit_move_insn (operands[7], CONST1_RTX (XFmode));  /* fld1 */
 })
 
+(define_expand "exp10sf2"
+  [(set (match_dup 2)
+	(float_extend:XF (match_operand:SF 1 "register_operand" "")))
+   (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
+   (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
+   (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
+   (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
+   (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
+   (parallel [(set (match_operand:SF 0 "register_operand" "")
+		   (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
+	      (clobber (match_scratch:SF 5 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  rtx temp;
+  int i;
+
+  for (i=2; i<10; i++)
+    operands[i] = gen_reg_rtx (XFmode);
+  temp = standard_80387_constant_rtx (6); /* fldl2t */
+  emit_move_insn (operands[3], temp);
+  emit_move_insn (operands[8], CONST1_RTX (XFmode));  /* fld1 */
+})
+
+(define_expand "exp10df2"
+  [(set (match_dup 2)
+	(float_extend:XF (match_operand:DF 1 "register_operand" "")))
+   (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
+   (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
+   (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
+   (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
+   (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
+   (parallel [(set (match_operand:DF 0 "register_operand" "")
+		   (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
+	      (clobber (match_scratch:DF 5 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  rtx temp;
+  int i;
+
+  for (i=2; i<10; i++)
+    operands[i] = gen_reg_rtx (XFmode);
+  temp = standard_80387_constant_rtx (6); /* fldl2t */
+  emit_move_insn (operands[3], temp);
+  emit_move_insn (operands[8], CONST1_RTX (XFmode));  /* fld1 */
+})
+
+(define_expand "exp10xf2"
+  [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
+			       (match_dup 2)))
+   (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
+   (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
+   (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
+   (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
+   (parallel [(set (match_operand:XF 0 "register_operand" "")
+		   (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
+	      (clobber (match_scratch:XF 5 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  rtx temp;
+  int i;
+
+  for (i=2; i<9; i++)
+    operands[i] = gen_reg_rtx (XFmode);
+  temp = standard_80387_constant_rtx (6); /* fldl2t */
+  emit_move_insn (operands[2], temp);
+  emit_move_insn (operands[7], CONST1_RTX (XFmode));  /* fld1 */
+})
+
+(define_expand "exp2sf2"
+  [(set (match_dup 2)
+	(float_extend:XF (match_operand:SF 1 "register_operand" "")))
+   (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
+   (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
+   (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
+   (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
+   (parallel [(set (match_operand:SF 0 "register_operand" "")
+		   (unspec:SF [(match_dup 7) (match_dup 3)] UNSPEC_FSCALE))
+	      (clobber (match_scratch:SF 3 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  int i;
+
+  for (i=2; i<8; i++)
+    operands[i] = gen_reg_rtx (XFmode);
+  emit_move_insn (operands[6], CONST1_RTX (XFmode));  /* fld1 */
+})
+
+(define_expand "exp2df2"
+  [(set (match_dup 2)
+	(float_extend:XF (match_operand:DF 1 "register_operand" "")))
+   (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
+   (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
+   (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
+   (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
+   (parallel [(set (match_operand:DF 0 "register_operand" "")
+		   (unspec:DF [(match_dup 7) (match_dup 3)] UNSPEC_FSCALE))
+	      (clobber (match_scratch:DF 3 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  int i;
+
+  for (i=2; i<8; i++)
+    operands[i] = gen_reg_rtx (XFmode);
+  emit_move_insn (operands[6], CONST1_RTX (XFmode));  /* fld1 */
+})
+
+(define_expand "exp2xf2"
+  [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
+   (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
+   (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
+   (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
+   (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
+   (parallel [(set (match_operand:XF 0 "register_operand" "")
+		   (unspec:XF [(match_dup 7) (match_dup 3)] UNSPEC_FSCALE))
+	      (clobber (match_scratch:XF 3 ""))])]
+  "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+   && flag_unsafe_math_optimizations"
+{
+  int i;
+
+  for (i=2; i<8; i++)
+    operands[i] = gen_reg_rtx (XFmode);
+  emit_move_insn (operands[6], CONST1_RTX (XFmode));  /* fld1 */
+})
+
 (define_expand "atansf2"
   [(parallel [(set (match_operand:SF 0 "register_operand" "")
 		   (unspec:SF [(match_dup 2)