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| author | H.J. Lu <hongjiu.lu@intel.com> | 2007-05-31 19:52:24 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2007-05-31 12:52:24 -0700 |
| commit | 3b8dd0716ff7c5411334c1f0ad61306ec97ac6e9 (patch) | |
| tree | af5f8a80f0f784ca8b3ed00d982749ac5b74a6e3 /gcc/config/i386/i386.md | |
| parent | ccb4d26be0082d11486c820ca78699c9e1332d23 (diff) | |
| download | gcc-3b8dd0716ff7c5411334c1f0ad61306ec97ac6e9.zip gcc-3b8dd0716ff7c5411334c1f0ad61306ec97ac6e9.tar.gz gcc-3b8dd0716ff7c5411334c1f0ad61306ec97ac6e9.tar.bz2 | |
config.gcc (i[34567]86-*-*): Add nmmintrin.h to extra_headers.
2007-05-31 H.J. Lu <hongjiu.lu@intel.com>
* config.gcc (i[34567]86-*-*): Add nmmintrin.h to
extra_headers.
(x86_64-*-*): Likewise.
* config/i386/i386.c (OPTION_MASK_ISA_MMX_UNSET): New.
(OPTION_MASK_ISA_3DNOW_UNSET): Likewise.
(OPTION_MASK_ISA_SSE_UNSET): Likewise.
(OPTION_MASK_ISA_SSE2_UNSET): Likewise.
(OPTION_MASK_ISA_SSE3_UNSET): Likewise.
(OPTION_MASK_ISA_SSSE3_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4_1_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4_2_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4): Likewise.
(OPTION_MASK_ISA_SSE4_UNSET): Likewise.
(OPTION_MASK_ISA_SSE4A_UNSET): Likewise.
(ix86_handle_option): Use OPTION_MASK_ISA_*_UNSET. Handle
SSE4.2.
(override_options): Support SSE4.2.
(ix86_build_const_vector): Support SImode and DImode.
(ix86_build_signbit_mask): Likewise.
(ix86_expand_int_vcond): Support V2DImode.
(IX86_BUILTIN_CRC32QI): New for SSE4.2.
(IX86_BUILTIN_CRC32HI): Likewise.
(IX86_BUILTIN_CRC32SI): Likewise.
(IX86_BUILTIN_CRC32DI): Likewise.
(IX86_BUILTIN_PCMPGTQ): Likewise.
(bdesc_crc32): Likewise.
(bdesc_sse_3arg): Likewise.
(ix86_expand_crc32): Likewise.
(ix86_init_mmx_sse_builtins): Support SSE4.2.
(ix86_expand_builtin): Likewise.
* config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Define
__SSE4_2__ for -msse4.2.
* config/i386/i386.md (UNSPEC_CRC32): New for SSE4.2.
(CRC32MODE): Likewise.
(crc32modesuffix): Likewise.
(crc32modeconstraint): Likewise.
(sse4_2_crc32<mode>): Likewise.
(sse4_2_crc32di): Likewise.
* config/i386/i386.opt (msse4.2): New for SSE4.2.
(msse4): Likewise.
* config/i386/nmmintrin.h: New. The dummy SSE4.2 intrinsic header
file.
* config/i386/smmintrin.h: Add SSE4.2 intrinsics.
* config/i386/sse.md (sse4_2_gtv2di3): New pattern for
SSE4.2.
(vcond<mode>): Use SSEMODEI instead of SSEMODE124.
(vcondu<mode>): Likewise.
* doc/extend.texi: Document SSE4.2 built-in functions.
* doc/invoke.texi: Document -msse4.2/-msse4.
From-SVN: r125236
Diffstat (limited to 'gcc/config/i386/i386.md')
| -rw-r--r-- | gcc/config/i386/i386.md | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3912fb6..38e41bc 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -173,6 +173,9 @@ (UNSPEC_PTEST 140) (UNSPEC_ROUNDP 141) (UNSPEC_ROUNDS 142) + + ; For SSE4.2 support + (UNSPEC_CRC32 143) ]) (define_constants @@ -20895,6 +20898,36 @@ } [(set_attr "type" "multi")]) +(define_mode_macro CRC32MODE [QI HI SI]) +(define_mode_attr crc32modesuffix [(QI "b") (HI "w") (SI "l")]) +(define_mode_attr crc32modeconstraint [(QI "qm") (HI "rm") (SI "rm")]) + +(define_insn "sse4_2_crc32<mode>" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI + [(match_operand:SI 1 "register_operand" "0") + (match_operand:CRC32MODE 2 "nonimmediate_operand" "<crc32modeconstraint>")] + UNSPEC_CRC32))] + "TARGET_SSE4_2" + "crc32<crc32modesuffix>\t{%2, %0|%0, %2}" + [(set_attr "type" "sselog1") + (set_attr "prefix_rep" "1") + (set_attr "prefix_extra" "1") + (set_attr "mode" "SI")]) + +(define_insn "sse4_2_crc32di" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI + [(match_operand:DI 1 "register_operand" "0") + (match_operand:DI 2 "nonimmediate_operand" "rm")] + UNSPEC_CRC32))] + "TARGET_SSE4_2 && TARGET_64BIT" + "crc32q\t{%2, %0|%0, %2}" + [(set_attr "type" "sselog1") + (set_attr "prefix_rep" "1") + (set_attr "prefix_extra" "1") + (set_attr "mode" "DI")]) + (include "mmx.md") (include "sse.md") (include "sync.md") |