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| author | Marc Glisse <marc.glisse@inria.fr> | 2012-10-08 22:45:56 +0200 |
|---|---|---|
| committer | Marc Glisse <glisse@gcc.gnu.org> | 2012-10-08 20:45:56 +0000 |
| commit | b790dea2eb93fa958ec9b3f62adbbb1d1e633d1e (patch) | |
| tree | ec8cd77b0fd2b7468d9a7a4fe327fae6147c4c15 /gcc/config/i386/athlon.md | |
| parent | 9b2770f22cfddf5a0ab54659ce696071b0857444 (diff) | |
| download | gcc-b790dea2eb93fa958ec9b3f62adbbb1d1e633d1e.zip gcc-b790dea2eb93fa958ec9b3f62adbbb1d1e633d1e.tar.gz gcc-b790dea2eb93fa958ec9b3f62adbbb1d1e633d1e.tar.bz2 | |
re PR middle-end/54400 (recognize vector reductions)
2012-10-08 Marc Glisse <marc.glisse@inria.fr>
gcc/
PR target/54400
* config/i386/i386.md (type attribute): Add sseadd1.
(unit attribute): Add support for sseadd1.
(memory attribute): Likewise.
* config/i386/athlon.md: Likewise.
* config/i386/core2.md: Likewise.
* config/i386/atom.md: Likewise.
* config/i386/ppro.md: Likewise.
* config/i386/bdver1.md: Likewise.
* config/i386/sse.md (sse3_h<plusminus_insn>v2df3): split into...
(sse3_haddv2df3): ... expander.
(*sse3_haddv2df3): ... define_insn. Accept permuted operands.
(sse3_hsubv2df3): ... define_insn.
(*sse3_haddv2df3_low): New define_insn.
(*sse3_hsubv2df3_low): New define_insn.
gcc/testsuite/
PR target/54400
* gcc.target/i386/pr54400.c: New testcase.
From-SVN: r192223
Diffstat (limited to 'gcc/config/i386/athlon.md')
| -rw-r--r-- | gcc/config/i386/athlon.md | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/gcc/config/i386/athlon.md b/gcc/config/i386/athlon.md index 401cb0d..1a2d607 100644 --- a/gcc/config/i386/athlon.md +++ b/gcc/config/i386/athlon.md @@ -807,47 +807,47 @@ "athlon-direct,athlon-fpsched,athlon-fadd") (define_insn_reservation "athlon_sseadd_load" 4 (and (eq_attr "cpu" "athlon") - (and (eq_attr "type" "sseadd") + (and (eq_attr "type" "sseadd,sseadd1") (and (eq_attr "mode" "SF,DF,DI") (eq_attr "memory" "load")))) "athlon-direct,athlon-fpload,athlon-fadd") (define_insn_reservation "athlon_sseadd_load_k8" 6 (and (eq_attr "cpu" "k8,generic64,amdfam10") - (and (eq_attr "type" "sseadd") + (and (eq_attr "type" "sseadd,sseadd1") (and (eq_attr "mode" "SF,DF,DI") (eq_attr "memory" "load")))) "athlon-direct,athlon-fploadk8,athlon-fadd") (define_insn_reservation "athlon_sseadd" 4 (and (eq_attr "cpu" "athlon,k8,generic64,amdfam10") - (and (eq_attr "type" "sseadd") + (and (eq_attr "type" "sseadd,sseadd1") (eq_attr "mode" "SF,DF,DI"))) "athlon-direct,athlon-fpsched,athlon-fadd") (define_insn_reservation "athlon_sseaddvector_load" 5 (and (eq_attr "cpu" "athlon") - (and (eq_attr "type" "sseadd") + (and (eq_attr "type" "sseadd,sseadd1") (eq_attr "memory" "load"))) "athlon-vector,athlon-fpload2,(athlon-fadd*2)") (define_insn_reservation "athlon_sseaddvector_load_k8" 7 (and (eq_attr "cpu" "k8,generic64") - (and (eq_attr "type" "sseadd") + (and (eq_attr "type" "sseadd,sseadd1") (eq_attr "memory" "load"))) "athlon-double,athlon-fpload2k8,(athlon-fadd*2)") (define_insn_reservation "athlon_sseaddvector_load_amdfam10" 6 (and (eq_attr "cpu" "amdfam10") - (and (eq_attr "type" "sseadd") + (and (eq_attr "type" "sseadd,sseadd1") (eq_attr "memory" "load"))) "athlon-direct,athlon-fploadk8,athlon-fadd") (define_insn_reservation "athlon_sseaddvector" 5 (and (eq_attr "cpu" "athlon") - (eq_attr "type" "sseadd")) + (eq_attr "type" "sseadd,sseadd1")) "athlon-vector,athlon-fpsched,(athlon-fadd*2)") (define_insn_reservation "athlon_sseaddvector_k8" 5 (and (eq_attr "cpu" "k8,generic64") - (eq_attr "type" "sseadd")) + (eq_attr "type" "sseadd,sseadd1")) "athlon-double,athlon-fpsched,(athlon-fadd*2)") (define_insn_reservation "athlon_sseaddvector_amdfam10" 4 (and (eq_attr "cpu" "amdfam10") - (eq_attr "type" "sseadd")) + (eq_attr "type" "sseadd,sseadd1")) "athlon-direct,athlon-fpsched,athlon-fadd") ;; Conversions behaves very irregularly and the scheduling is critical here. |