Use proper modes and predicates for {sign,zero}_extract.

From-SVN: r11511

1 files changed, 64 insertions, 40 deletions

diff --git a/gcc/config/fx80/fx80.md b/gcc/config/fx80/fx80.md
index d12fb58..6862767 100644
--- a/gcc/config/fx80/fx80.md
+++ b/gcc/config/fx80/fx80.md
@@ -1,5 +1,5 @@
 ;;- Machine description for GNU C compiler for Alliant FX systems
-;;  Copyright (C) 1989, 1994 Free Software Foundation, Inc.
+;;  Copyright (C) 1989, 1994, 1996 Free Software Foundation, Inc.
 ;;  Adapted from m68k.md by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
 ;;  and Joe Weening (weening@gang-of-four.stanford.edu).
 
@@ -195,7 +195,7 @@
 ;; Recognizers for btst instructions.
 
 (define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
 			    (const_int 1)
 			    (minus:SI (const_int 7)
 				      (match_operand:SI 1 "general_operand" "di"))))]
@@ -203,7 +203,7 @@
   "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
 
 (define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
 			    (const_int 1)
 			    (minus:SI (const_int 31)
 				      (match_operand:SI 1 "general_operand" "di"))))]
@@ -215,7 +215,7 @@
 ;; are automatically masked to 3 or 5 bits.
 
 (define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
+  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
 			    (const_int 1)
 			    (minus:SI (const_int 7)
 				      (and:SI
@@ -225,7 +225,7 @@
   "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
 
 (define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
+  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
 			    (const_int 1)
 			    (minus:SI (const_int 31)
 				      (and:SI
@@ -237,7 +237,7 @@
 ;; Nonoffsettable mem refs are ok in this one pattern
 ;; since we don't try to adjust them.
 (define_insn ""
-  [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
+  [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
 			    (const_int 1)
 			    (match_operand:SI 1 "general_operand" "i")))]
   "GET_CODE (operands[1]) == CONST_INT
@@ -250,7 +250,7 @@
 
 
 (define_insn ""
-  [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
+  [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
 			    (const_int 1)
 			    (match_operand:SI 1 "general_operand" "i")))]
   "GET_CODE (operands[1]) == CONST_INT"
@@ -1656,7 +1656,7 @@
 ;; which can usually be done with move instructions.
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
 			 (match_operand:SI 1 "const_int_operand" "i")
 			 (match_operand:SI 2 "const_int_operand" "i"))
 	(match_operand:SI 3 "general_operand" "d"))]
@@ -1686,7 +1686,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=&d")
-	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "do")
 			 (match_operand:SI 2 "const_int_operand" "i")
 			 (match_operand:SI 3 "const_int_operand" "i")))]
   "TARGET_68020 && TARGET_BITFIELD
@@ -1716,7 +1716,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
+	(sign_extract:SI (match_operand:SI 1 "register_operand" "do")
 			 (match_operand:SI 2 "const_int_operand" "i")
 			 (match_operand:SI 3 "const_int_operand" "i")))]
   "TARGET_68020 && TARGET_BITFIELD
@@ -1744,26 +1744,42 @@
 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
 ;; so that its address is reloaded.
 
-(define_insn "extv"
-  [(set (match_operand:SI 0 "general_operand" "=d,d")
-	(sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
-			 (match_operand:SI 2 "general_operand" "di,di")
-			 (match_operand:SI 3 "general_operand" "di,di")))]
+(define_expand "extv"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(sign_extract:SI (match_operand:SI 1 "general_operand" "")
+			 (match_operand:SI 2 "general_operand" "")
+			 (match_operand:SI 3 "general_operand" "")))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
+			 (match_operand:SI 2 "general_operand" "di")
+			 (match_operand:SI 3 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"
   "bfexts [%c3,%c2]%1,%0")
 
-(define_insn "extzv"
-  [(set (match_operand:SI 0 "general_operand" "=d,d")
-	(zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
-			 (match_operand:SI 2 "general_operand" "di,di")
-			 (match_operand:SI 3 "general_operand" "di,di")))]
+(define_expand "extzv"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(zero_extract:SI (match_operand:SI 1 "general_operand" "")
+			 (match_operand:SI 2 "general_operand" "")
+			 (match_operand:SI 3 "general_operand" "")))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "general_operand" "=d")
+	(zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
+			 (match_operand:SI 2 "general_operand" "di")
+			 (match_operand:SI 3 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"
   "bfextu [%c3,%c2]%1,%0")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
-			 (match_operand:SI 1 "general_operand" "di,di")
-			 (match_operand:SI 2 "general_operand" "di,di"))
+  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 2 "general_operand" "di"))
         (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
 		(match_operand:SI 3 "const_int_operand" "i,i")))]
   "TARGET_68020 && TARGET_BITFIELD
@@ -1777,9 +1793,9 @@
 }")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
-			 (match_operand:SI 1 "general_operand" "di,di")
-			 (match_operand:SI 2 "general_operand" "di,di"))
+  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 2 "general_operand" "di"))
 	(const_int 0))]
   "TARGET_68020 && TARGET_BITFIELD"
   "*
@@ -1789,9 +1805,9 @@
 }")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
-			 (match_operand:SI 1 "general_operand" "di,di")
-			 (match_operand:SI 2 "general_operand" "di,di"))
+  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 2 "general_operand" "di"))
 	(const_int -1))]
   "TARGET_68020 && TARGET_BITFIELD"
   "*
@@ -1800,11 +1816,19 @@
   return \"bfset [%c2,%c1]%0\";
 }")
 
-(define_insn "insv"
-  [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
-			 (match_operand:SI 1 "general_operand" "di,di")
-			 (match_operand:SI 2 "general_operand" "di,di"))
-	(match_operand:SI 3 "general_operand" "d,d"))]
+(define_expand "insv"
+  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
+			 (match_operand:SI 1 "general_operand" "")
+			 (match_operand:SI 2 "general_operand" ""))
+	(match_operand:SI 3 "general_operand" ""))]
+  "TARGET_68020 && TARGET_BITFIELD"
+  "")
+
+(define_insn ""
+  [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
+			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 2 "general_operand" "di"))
+	(match_operand:SI 3 "general_operand" "d"))]
   "TARGET_68020 && TARGET_BITFIELD"
   "bfins %3,[%c2,%c1]%0")
 
@@ -1813,7 +1837,7 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=d")
-	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+	(sign_extract:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "general_operand" "di")
 			 (match_operand:SI 3 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"
@@ -1821,14 +1845,14 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=d")
-	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
+	(zero_extract:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "general_operand" "di")
 			 (match_operand:SI 3 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"
   "bfextu [%c3,%c2]%1,%0")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
 			 (match_operand:SI 1 "general_operand" "di")
 			 (match_operand:SI 2 "general_operand" "di"))
 	(const_int 0))]
@@ -1840,7 +1864,7 @@
 }")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
 			 (match_operand:SI 1 "general_operand" "di")
 			 (match_operand:SI 2 "general_operand" "di"))
 	(const_int -1))]
@@ -1852,7 +1876,7 @@
 }")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
 			 (match_operand:SI 1 "general_operand" "di")
 			 (match_operand:SI 2 "general_operand" "di"))
 	(match_operand:SI 3 "general_operand" "d"))]
@@ -1893,7 +1917,7 @@
 ;;; now handle the register cases
 (define_insn ""
   [(set (cc0)
-	(zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
+	(zero_extract:SI (match_operand:SI 0 "register_operand" "d")
 			 (match_operand:SI 1 "const_int_operand" "i")
 			 (match_operand:SI 2 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"