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| author | Bernd Schmidt <bernd.schmidt@analog.com> | 2007-09-13 18:27:28 +0000 |
|---|---|---|
| committer | Bernd Schmidt <bernds@gcc.gnu.org> | 2007-09-13 18:27:28 +0000 |
| commit | 1d7d5ac4e8c62c26923e0a747afe5df3f5d13011 (patch) | |
| tree | 9d4f5512db93d9d4b82adb7caef6f9d5026eaadf /gcc/config/bfin/bfin.md | |
| parent | eae8e4741e77af8d8b496c86d74a4b7161e3ccc6 (diff) | |
| download | gcc-1d7d5ac4e8c62c26923e0a747afe5df3f5d13011.zip gcc-1d7d5ac4e8c62c26923e0a747afe5df3f5d13011.tar.gz gcc-1d7d5ac4e8c62c26923e0a747afe5df3f5d13011.tar.bz2 | |
From Jie Zhang:
* config/bfin/bfin.c (enum bfin_builtins): Add BFIN_BUILTIN_ONES,
BFIN_BUILTIN_CPLX_MUL_16_S40, BFIN_BUILTIN_CPLX_MAC_16_S40,
BFIN_BUILTIN_CPLX_MSU_16_S40, and BFIN_BUILTIN_CPLX_SQU.
(bfin_init_builtins): Initialize __builtin_bfin_ones,
__builtin_bfin_min_fr1x16, __builtin_bfin_max_fr1x16,
__builtin_bfin_min_fr1x32, __builtin_bfin_max_fr1x32,
__builtin_bfin_cmplx_add, __builtin_bfin_cmplx_sub,
__builtin_bfin_cmplx_mul_s40, __builtin_bfin_cmplx_mac_s40,
__builtin_bfin_cmplx_msu_s40 and __builtin_bfin_csqu_fr16.
(bdesc_1arg): Add __builtin_bfin_ones.
(bfin_expand_builtin): Expand __builtin_bfin_cmplx_mul_s40,
__builtin_bfin_cmplx_mac_s40, __builtin_bfin_cmplx_msu_s40,
and __builtin_bfin_csqu_fr16.
* config/bfin/bfin.md (UNSPEC_ONES): New constant.
(ones): New define_insn.
(ssaddhi3_parts): New define_insn.
(sssubhi3_parts): New define_insn.
(flag_mulhi_parts): New define_insn.
From-SVN: r128475
Diffstat (limited to 'gcc/config/bfin/bfin.md')
| -rw-r--r-- | gcc/config/bfin/bfin.md | 94 |
1 files changed, 93 insertions, 1 deletions
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md index 0184999..b2a73f1 100644 --- a/gcc/config/bfin/bfin.md +++ b/gcc/config/bfin/bfin.md @@ -137,7 +137,8 @@ (UNSPEC_LSETUP_END 10) ;; Distinguish a 32-bit version of an insn from a 16-bit version. (UNSPEC_32BIT 11) - (UNSPEC_NOP 12)]) + (UNSPEC_NOP 12) + (UNSPEC_ONES 12)]) (define_constants [(UNSPEC_VOLATILE_EH_RETURN 0) @@ -1314,6 +1315,14 @@ %0 = %1 ^ %2;" [(set_attr "type" "alu0")]) +(define_insn "ones" + [(set (match_operand:HI 0 "register_operand" "=d") + (unspec:HI [(match_operand:SI 1 "register_operand" "d")] + UNSPEC_ONES))] + "" + "%h0 = ONES %1;" + [(set_attr "type" "alu0")]) + (define_insn "smaxsi3" [(set (match_operand:SI 0 "register_operand" "=d") (smax:SI (match_operand:SI 1 "register_operand" "d") @@ -2943,6 +2952,60 @@ "%h0 = %h1 + %h2 (S)%!" [(set_attr "type" "dsp32")]) +(define_insn "ssaddhi3_parts" + [(set (vec_select:HI + (match_operand:V2HI 0 "register_operand" "d") + (parallel [(match_operand 3 "const01_operand" "P0P1")])) + (ss_plus:HI (vec_select:HI + (match_operand:V2HI 1 "register_operand" "d") + (parallel [(match_operand 4 "const01_operand" "P0P1")])) + (vec_select:HI + (match_operand:V2HI 2 "register_operand" "d") + (parallel [(match_operand 5 "const01_operand" "P0P1")]))))] + "" +{ + const char *templates[] = { + "%h0 = %h1 + %h2 (S)%!", + "%d0 = %h1 + %h2 (S)%!", + "%h0 = %d1 + %h2 (S)%!", + "%d0 = %d1 + %h2 (S)%!", + "%h0 = %h1 + %d2 (S)%!", + "%d0 = %h1 + %d2 (S)%!", + "%h0 = %d1 + %d2 (S)%!", + "%d0 = %d1 + %d2 (S)%!" }; + int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) + + (INTVAL (operands[5]) << 2); + return templates[alt]; +} + [(set_attr "type" "dsp32")]) + +(define_insn "sssubhi3_parts" + [(set (vec_select:HI + (match_operand:V2HI 0 "register_operand" "d") + (parallel [(match_operand 3 "const01_operand" "P0P1")])) + (ss_minus:HI (vec_select:HI + (match_operand:V2HI 1 "register_operand" "d") + (parallel [(match_operand 4 "const01_operand" "P0P1")])) + (vec_select:HI + (match_operand:V2HI 2 "register_operand" "d") + (parallel [(match_operand 5 "const01_operand" "P0P1")]))))] + "" +{ + const char *templates[] = { + "%h0 = %h1 - %h2 (S)%!", + "%d0 = %h1 - %h2 (S)%!", + "%h0 = %d1 - %h2 (S)%!", + "%d0 = %d1 - %h2 (S)%!", + "%h0 = %h1 - %d2 (S)%!", + "%d0 = %h1 - %d2 (S)%!", + "%h0 = %d1 - %d2 (S)%!", + "%d0 = %d1 - %d2 (S)%!" }; + int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) + + (INTVAL (operands[5]) << 2); + return templates[alt]; +} + [(set_attr "type" "dsp32")]) + (define_insn "sssubhi3" [(set (match_operand:HI 0 "register_operand" "=d") (ss_minus:HI (match_operand:HI 1 "register_operand" "d") @@ -3157,6 +3220,35 @@ "%h0 = %h1 * %h2 %M3%!" [(set_attr "type" "dsp32")]) +(define_insn "flag_mulhi_parts" + [(set (vec_select:HI + (match_operand:V2HI 0 "register_operand" "d") + (parallel [(match_operand 3 "const01_operand" "P0P1")])) + (unspec:HI [(vec_select:HI + (match_operand:V2HI 1 "register_operand" "d") + (parallel [(match_operand 4 "const01_operand" "P0P1")])) + (vec_select:HI + (match_operand:V2HI 2 "register_operand" "d") + (parallel [(match_operand 5 "const01_operand" "P0P1")])) + (match_operand 6 "const_int_operand" "n")] + UNSPEC_MUL_WITH_FLAG))] + "" +{ + const char *templates[] = { + "%h0 = %h1 * %h2 %M6%!", + "%d0 = %h1 * %h2 %M6%!", + "%h0 = %d1 * %h2 %M6%!", + "%d0 = %d1 * %h2 %M6%!", + "%h0 = %h1 * %d2 %M6%!", + "%d0 = %h1 * %d2 %M6%!", + "%h0 = %d1 * %d2 %M6%!", + "%d0 = %d1 * %d2 %M6%!" }; + int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1) + + (INTVAL (operands[5]) << 2); + return templates[alt]; +} + [(set_attr "type" "dsp32")]) + (define_insn "flag_mulhisi" [(set (match_operand:SI 0 "register_operand" "=d") (unspec:SI [(match_operand:HI 1 "register_operand" "d") |