AVR cc0 conversion

See https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html
for background.

This patch converts the avr backend to MODE_CC. It addresses some of
the comments made in the previous submission over here
(https://gcc.gnu.org/pipermail/gcc-patches/2020-December/561757.html).

Specifically, this patch has

1. Automatic clobber of REG_CC in inline asm statements, via
TARGET_MD_ASM_ADJUST hook.

2. Direct clobber of REG_CC in insns emitted after reload (pro and
epilogue).

3. Regression testing done on atmega8, atmega128, attiny40 and
atxmega128a3 devices (more details below).

4. Verification and fixes for casesi and avr_compare_pattern related
code that inspects insns, by looking at avr-casesi and mach RTL dumps.

5. Use length of parallel instead of passing in operand counts when
generating code for shift patterns.

6. Fixes for indentation glitches.

7. Removal of CC_xxx stuff in avr-protos.h. In the places where the
macros were still used (cond_string), I've replaced them with a bool
hardcoded to false. I expect this will go away/get fixed when I
eventually add specific CC modes.

Things still to do:

1. Adjustment of peepholes/define_splits to match against patterns
   with REG_CC clobber.
2. Model effect of non-compare insns on REG_CC using additional CC
   modes. I'm hoping to use of a modified version of the cc attribute
   and define_subst (again inspired by the cris port), to do this.
3. RTX cost adjustment.

gcc/
	* config/avr/avr-dimode.md: Turn existing patterns into
	define_insn_and_split style patterns where the splitter
	adds a clobber of the condition code register.  Drop "cc"
	attribute.  Add new patterns to match output of
	the splitters.
	* config/avr/avr-fixed.md: Likewise.
	* config/avr/avr.c (cc_reg_rtx): New.
	(avr_parallel_insn_from_insns): Adjust insn count
	for removal of set of cc0.
	(avr_is_casesi_sequence): Likewise.
	(avr_casei_sequence_check_operands): Likewise.
	(avr_optimize_casesi): Likewise. Also insert
	new insns after jump_insn.
	(avr_pass_casesi::avr_rest_of_handle_casesi): Adjust
	for removal of set of cc0.
	(avr_init_expanders): Initialize cc_reg_rtx.
	(avr_regno_reg_class): Handle REG_CC.
	(cond_string): Remove usage of CC_OVERFLOW_UNUSABLE.
	(avr_notice_update_cc): Remove function.
	(ret_cond_branch): Remove usage of CC_OVERFLOW_UNUSABLE.
	(compare_condition): Adjust for PARALLEL with
	REG_CC clobber.
	(out_shift_with_cnt): Likewise.
	(ashlhi3_out): Likewise.
	(ashrhi3_out): Likewise.
	(lshrhi3_out): Likewise.
	(avr_class_max_nregs): Return single reg for REG_CC.
	(avr_compare_pattern): Check for REG_CC instead
	of cc0_rtx.
	(avr_reorg_remove_redundant_compare): Likewise.
	(avr_reorg):Adjust for PARALLEL with REG_CC clobber.
	(avr_hard_regno_nregs): Return single reg for REG_CC.
	(avr_hard_regno_mode_ok): Allow only CCmode for REG_CC.
	(avr_md_asm_adjust): Clobber REG_CC.
	(TARGET_HARD_REGNO_NREGS): Define.
	(TARGET_CLASS_MAX_NREGS): Define.
	(TARGET_MD_ASM_ADJUST): Define.
	* config/avr/avr.h (FIRST_PSEUDO_REGISTER): Adjust
	for REG_CC.
	(enum reg_class): Add CC_REG class.
	(NOTICE_UPDATE_CC): Remove.
	(CC_OVERFLOW_UNUSABLE): Remove.
	(CC_NO_CARRY): Remove.
	* config/avr/avr.md: Turn existing patterns into
	define_insn_and_split style patterns where the splitter
	adds a clobber of the condition code register.  Drop "cc"
	attribute.  Add new patterns to match output of
	the splitters.
	(sez): Remove unused pattern.

1 files changed, 11 insertions, 23 deletions

diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h
index 0026a66..30ce2ba 100644
--- a/gcc/config/avr/avr.h
+++ b/gcc/config/avr/avr.h
@@ -155,7 +155,7 @@ FIXME: DRIVER_SELF_SPECS has changed.
 
 #define WCHAR_TYPE_SIZE 16
 
-#define FIRST_PSEUDO_REGISTER 36
+#define FIRST_PSEUDO_REGISTER 37
 
 #define GENERAL_REGNO_P(N)	IN_RANGE (N, 2, 31)
 #define GENERAL_REG_P(X)	(REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
@@ -178,7 +178,8 @@ FIXME: DRIVER_SELF_SPECS has changed.
   0,0,/* r28 r29 */\
   0,0,/* r30 r31 */\
   1,1,/*  STACK */\
-  1,1 /* arg pointer */  }
+  1,1, /* arg pointer */						\
+  1 /* CC */ }
 
 #define CALL_USED_REGISTERS {			\
   1,1,/* r0 r1 */				\
@@ -198,7 +199,8 @@ FIXME: DRIVER_SELF_SPECS has changed.
     0,0,/* r28 r29 */				\
     1,1,/* r30 r31 */				\
     1,1,/*  STACK */				\
-    1,1 /* arg pointer */  }
+    1,1, /* arg pointer */			\
+    1 /* CC */ }
 
 #define REG_ALLOC_ORDER {			\
     24,25,					\
@@ -210,7 +212,7 @@ FIXME: DRIVER_SELF_SPECS has changed.
     28,29,					\
     17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,	\
     0,1,					\
-    32,33,34,35					\
+    32,33,34,35,36			\
     }
 
 #define ADJUST_REG_ALLOC_ORDER avr_adjust_reg_alloc_order()
@@ -230,6 +232,7 @@ enum reg_class {
   LD_REGS,			/* r16 - r31 */
   NO_LD_REGS,			/* r0 - r15 */
   GENERAL_REGS,			/* r0 - r31 */
+  CC_REG,			/* CC */
   ALL_REGS, LIM_REG_CLASSES
 };
 
@@ -250,6 +253,7 @@ enum reg_class {
 		   "LD_REGS",	/* r16 - r31 */			\
                    "NO_LD_REGS", /* r0 - r15 */                 \
 		   "GENERAL_REGS", /* r0 - r31 */		\
+		   "CC_REG", /* CC */		\
 		   "ALL_REGS" }
 
 #define REG_CLASS_CONTENTS {						\
@@ -270,7 +274,8 @@ enum reg_class {
      0x00000000},	/* LD_REGS, r16 - r31 */			\
   {0x0000ffff,0x00000000},	/* NO_LD_REGS  r0 - r15 */              \
   {0xffffffff,0x00000000},	/* GENERAL_REGS, r0 - r31 */		\
-  {0xffffffff,0x00000003}	/* ALL_REGS */				\
+  {0x00000000,0x00000010},	/* CC */				\
+  {0xffffffff,0x00000013}	/* ALL_REGS */				\
 }
 
 #define REGNO_REG_CLASS(R) avr_regno_reg_class(R)
@@ -429,7 +434,7 @@ typedef struct avr_args
     "r8","r9","r10","r11","r12","r13","r14","r15",	\
     "r16","r17","r18","r19","r20","r21","r22","r23",	\
     "r24","r25","r26","r27","r28","r29","r30","r31",	\
-    "__SP_L__","__SP_H__","argL","argH"}
+    "__SP_L__","__SP_H__","argL","argH", "cc"}
 
 #define FINAL_PRESCAN_INSN(insn, operand, nop)  \
   avr_final_prescan_insn (insn, operand,nop)
@@ -484,23 +489,6 @@ typedef struct avr_args
 
 #define TRAMPOLINE_SIZE 4
 
-/* Store in cc_status the expressions
-   that the condition codes will describe
-   after execution of an instruction whose pattern is EXP.
-   Do not alter them if the instruction would not alter the cc's.  */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) avr_notice_update_cc (EXP, INSN)
-
-/* The add insns don't set overflow in a usable way.  */
-#define CC_OVERFLOW_UNUSABLE 01000
-/* The mov,and,or,xor insns don't set carry.  That's ok though as the
-   Z bit is all we need when doing unsigned comparisons on the result of
-   these insns (since they're always with 0).  However, conditions.h has
-   CC_NO_OVERFLOW defined for this purpose.  Rename it to something more
-   understandable.  */
-#define CC_NO_CARRY CC_NO_OVERFLOW
-
-
 /* Output assembler code to FILE to increment profiler label # LABELNO
    for profiling a function entry.  */