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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2017-03-13 10:58:48 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2017-03-13 10:58:48 +0000 |
| commit | b8c3660369aba863d8149c046863d4974f8c9f56 (patch) | |
| tree | b534bdbf1a9db313f2ea2e3d9c6cf31d527c1f2b /gcc/config/arm | |
| parent | 91cd87db7e4a053f884f8e10e267e0f8913b988e (diff) | |
| download | gcc-b8c3660369aba863d8149c046863d4974f8c9f56.zip gcc-b8c3660369aba863d8149c046863d4974f8c9f56.tar.gz gcc-b8c3660369aba863d8149c046863d4974f8c9f56.tar.bz2 | |
[ARM] PR target/79911: Invalid vec_select arguments
PR target/79911
* config/arm/neon.md (vec_sel_widen_ssum_lo<VQI:mode><VW:mode>3):
Rename to...
(vec_sel_widen_ssum_lo<mode><V_half>3): ... This. Avoid mismatch
between vec_select and vector argument.
(vec_sel_widen_ssum_hi<VQI:mode><VW:mode>3): Rename to...
(vec_sel_widen_ssum_hi<mode><V_half>3): ... This. Likewise.
(vec_sel_widen_usum_lo<VQI:mode><VW:mode>3): Rename to...
(vec_sel_widen_usum_lo<mode><V_half>3): ... This.
(vec_sel_widen_usum_hi<VQI:mode><VW:mode>3): Rename to...
(vec_sel_widen_usum_hi<mode><V_half>3): ... This.
From-SVN: r246084
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/neon.md | 50 |
1 files changed, 26 insertions, 24 deletions
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index cf281df..50d89eb 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1335,14 +1335,14 @@ } ) -(define_insn "vec_sel_widen_ssum_lo<VQI:mode><VW:mode>3" - [(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w") - (plus:<VW:V_widen> - (sign_extend:<VW:V_widen> - (vec_select:VW +(define_insn "vec_sel_widen_ssum_lo<mode><V_half>3" + [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w") + (plus:<V_double_width> + (sign_extend:<V_double_width> + (vec_select:<V_HALF> (match_operand:VQI 1 "s_register_operand" "%w") (match_operand:VQI 2 "vect_par_constant_low" ""))) - (match_operand:<VW:V_widen> 3 "s_register_operand" "0")))] + (match_operand:<V_double_width> 3 "s_register_operand" "0")))] "TARGET_NEON" { return BYTES_BIG_ENDIAN ? "vaddw.<V_s_elem>\t%q0, %q3, %f1" : @@ -1350,13 +1350,14 @@ } [(set_attr "type" "neon_add_widen")]) -(define_insn "vec_sel_widen_ssum_hi<VQI:mode><VW:mode>3" - [(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w") - (plus:<VW:V_widen> - (sign_extend:<VW:V_widen> - (vec_select:VW (match_operand:VQI 1 "s_register_operand" "%w") +(define_insn "vec_sel_widen_ssum_hi<mode><V_half>3" + [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w") + (plus:<V_double_width> + (sign_extend:<V_double_width> + (vec_select:<V_HALF> + (match_operand:VQI 1 "s_register_operand" "%w") (match_operand:VQI 2 "vect_par_constant_high" ""))) - (match_operand:<VW:V_widen> 3 "s_register_operand" "0")))] + (match_operand:<V_double_width> 3 "s_register_operand" "0")))] "TARGET_NEON" { return BYTES_BIG_ENDIAN ? "vaddw.<V_s_elem>\t%q0, %q3, %e1" : @@ -1404,14 +1405,14 @@ } ) -(define_insn "vec_sel_widen_usum_lo<VQI:mode><VW:mode>3" - [(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w") - (plus:<VW:V_widen> - (zero_extend:<VW:V_widen> - (vec_select:VW +(define_insn "vec_sel_widen_usum_lo<mode><V_half>3" + [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w") + (plus:<V_double_width> + (zero_extend:<V_double_width> + (vec_select:<V_HALF> (match_operand:VQI 1 "s_register_operand" "%w") (match_operand:VQI 2 "vect_par_constant_low" ""))) - (match_operand:<VW:V_widen> 3 "s_register_operand" "0")))] + (match_operand:<V_double_width> 3 "s_register_operand" "0")))] "TARGET_NEON" { return BYTES_BIG_ENDIAN ? "vaddw.<V_u_elem>\t%q0, %q3, %f1" : @@ -1419,13 +1420,14 @@ } [(set_attr "type" "neon_add_widen")]) -(define_insn "vec_sel_widen_usum_hi<VQI:mode><VW:mode>3" - [(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w") - (plus:<VW:V_widen> - (zero_extend:<VW:V_widen> - (vec_select:VW (match_operand:VQI 1 "s_register_operand" "%w") +(define_insn "vec_sel_widen_usum_hi<mode><V_half>3" + [(set (match_operand:<V_double_width> 0 "s_register_operand" "=w") + (plus:<V_double_width> + (zero_extend:<V_double_width> + (vec_select:<V_HALF> + (match_operand:VQI 1 "s_register_operand" "%w") (match_operand:VQI 2 "vect_par_constant_high" ""))) - (match_operand:<VW:V_widen> 3 "s_register_operand" "0")))] + (match_operand:<V_double_width> 3 "s_register_operand" "0")))] "TARGET_NEON" { return BYTES_BIG_ENDIAN ? "vaddw.<V_u_elem>\t%q0, %q3, %e1" : |