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author | Terry Guo <terry.guo@arm.com> | 2013-04-17 06:24:48 +0000 |
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committer | Xuepeng Guo <xguo@gcc.gnu.org> | 2013-04-17 06:24:48 +0000 |
commit | 10a883113b6d5657efeb9d3eedef1a13f97185f3 (patch) | |
tree | c56157f9ef28918ce773b2483ed624fd3547497b /gcc/config/arm | |
parent | f3d096b0a87770fc3efe647f3b6de136479206ab (diff) | |
download | gcc-10a883113b6d5657efeb9d3eedef1a13f97185f3.zip gcc-10a883113b6d5657efeb9d3eedef1a13f97185f3.tar.gz gcc-10a883113b6d5657efeb9d3eedef1a13f97185f3.tar.bz2 |
* config/arm/cortex-m4.md: Add a new bypass.
From-SVN: r198021
Diffstat (limited to 'gcc/config/arm')
-rw-r--r-- | gcc/config/arm/cortex-m4.md | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 187867b..47b0364 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -84,6 +84,10 @@ (eq_attr "type" "store4")) "cortex_m4_ex*5") +(define_bypass 1 "cortex_m4_load1" + "cortex_m4_store1_1,cortex_m4_store1_2" + "arm_no_early_store_addr_dep") + ;; If the address of load or store depends on the result of the preceding ;; instruction, the latency is increased by one. |