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| author | Alex Velenko <Alex.Velenko@arm.com> | 2015-05-18 14:38:41 +0000 |
|---|---|---|
| committer | Alex Velenko <avelenko@gcc.gnu.org> | 2015-05-18 14:38:41 +0000 |
| commit | 0454e698401a3ec49700e59855e44493ab9fdbdb (patch) | |
| tree | 215a5650df3111f0512228a840f449d017333e50 /gcc/config/arm | |
| parent | fb05f2e4ddc9ae051cf205eb7eaa0e0e63cecf6c (diff) | |
| download | gcc-0454e698401a3ec49700e59855e44493ab9fdbdb.zip gcc-0454e698401a3ec49700e59855e44493ab9fdbdb.tar.gz gcc-0454e698401a3ec49700e59855e44493ab9fdbdb.tar.bz2 | |
arm.md (andsi_not_shiftsi_si_scc): New pattern.
gcc/config
2015-05-18 Alex Velenko <Alex.Velenko@arm.com>
* arm/arm.md (andsi_not_shiftsi_si_scc): New pattern.
(andsi_not_shiftsi_si_scc_no_reuse): New pattern.
gcc/testsuite
2015-05-18 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/arm/bics_1.c : New testcase.
* gcc.target/arm/bics_2.c : New testcase.
* gcc.target/arm/bics_3.c : New testcase.
* gcc.target/arm/bics_4.c : New testcase.
From-SVN: r223295
Diffstat (limited to 'gcc/config/arm')
| -rw-r--r-- | gcc/config/arm/arm.md | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9a71b79..191f5e7 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -2783,6 +2783,55 @@ (const_string "logic_shift_reg")))] ) +;; Shifted bics pattern used to set up CC status register and not reusing +;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2 +;; does not support shift by register. +(define_insn "andsi_not_shiftsi_si_scc_no_reuse" + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV + (and:SI (not:SI (match_operator:SI 0 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_rhs_operand" "rM")])) + (match_operand:SI 3 "s_register_operand" "r")) + (const_int 0))) + (clobber (match_scratch:SI 4 "=r"))] + "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))" + "bic%.%?\\t%4, %3, %1%S0" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "conds" "set") + (set_attr "shift" "1") + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "logic_shift_imm") + (const_string "logic_shift_reg")))] +) + +;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also +;; getting reused later. +(define_insn "andsi_not_shiftsi_si_scc" + [(parallel [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV + (and:SI (not:SI (match_operator:SI 0 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_rhs_operand" "rM")])) + (match_operand:SI 3 "s_register_operand" "r")) + (const_int 0))) + (set (match_operand:SI 4 "s_register_operand" "=r") + (and:SI (not:SI (match_op_dup 0 + [(match_dup 1) + (match_dup 2)])) + (match_dup 3)))])] + "TARGET_ARM || (TARGET_THUMB2 && CONST_INT_P (operands[2]))" + "bic%.%?\\t%4, %3, %1%S0" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "conds" "set") + (set_attr "shift" "1") + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "logic_shift_imm") + (const_string "logic_shift_reg")))] +) + (define_insn "*andsi_notsi_si_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV |