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| author | Dennis Zhang <dennis.zh@live.com> | 2020-10-23 08:53:53 +0100 |
|---|---|---|
| committer | Dennis Zhang <dennis.zh@live.com> | 2020-10-23 08:53:53 +0100 |
| commit | 98161c248c88f873bbffba23664c540f551d89d5 (patch) | |
| tree | 85788a59de2faac58f11a54183b20d7717a31bb0 /gcc/config/arm/vec-common.md | |
| parent | 6fade5a6044b7102758f4ca66c8715ebc12a6306 (diff) | |
| download | gcc-98161c248c88f873bbffba23664c540f551d89d5.zip gcc-98161c248c88f873bbffba23664c540f551d89d5.tar.gz gcc-98161c248c88f873bbffba23664c540f551d89d5.tar.bz2 | |
arm: Auto-vectorization for MVE: vsub
This patch enables MVE vsub instructions for auto-vectorization.
The sub<mode>3 in vec-common.md is modified to use new mode macros
to include MVE extension for vectorization. MVE vsub insns in mve.md are
modified to use 'minus' instead of unspec expression to support
sub<mode>3. Use VDQ instead fo VALL to cover all supported modes. The
redundant sub<mode>3 insns in neon.md are then removed.
gcc/ChangeLog:
2020-10-23 Dennis Zhang <dennis.zhang@arm.com>
* config/arm/mve.md (mve_vsubq<mode>): New entry for vsub instruction
using expression 'minus'.
(mve_vsubq_f<mode>): Use minus instead of VSUBQ_F unspec.
* config/arm/neon.md (sub<mode>3, sub<mode>3_fp16): Removed.
(neon_vsub<mode>): Use gen_sub<mode>3 instead of gen_sub<mode>3_fp16.
* config/arm/vec-common.md (sub<mode>3): Use the new mode macros
ARM_HAVE_<MODE>_ARITH. Use iterator VDQ instead of VALL.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/mve-vsub_1.c: New test.
Diffstat (limited to 'gcc/config/arm/vec-common.md')
| -rw-r--r-- | gcc/config/arm/vec-common.md | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 0f117d6..250e503 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -87,18 +87,12 @@ "ARM_HAVE_<MODE>_ARITH" ) -;; Vector arithmetic. Expanders are blank, then unnamed insns implement -;; patterns separately for IWMMXT and Neon. - (define_expand "sub<mode>3" - [(set (match_operand:VALL 0 "s_register_operand") - (minus:VALL (match_operand:VALL 1 "s_register_operand") - (match_operand:VALL 2 "s_register_operand")))] - "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) - || flag_unsafe_math_optimizations)) - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" -{ -}) + [(set (match_operand:VDQ 0 "s_register_operand") + (minus:VDQ (match_operand:VDQ 1 "s_register_operand") + (match_operand:VDQ 2 "s_register_operand")))] + "ARM_HAVE_<MODE>_ARITH" +) (define_expand "mul<mode>3" [(set (match_operand:VDQWH 0 "s_register_operand") |