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| author | Sudakshina Das <sudi.das@arm.com> | 2018-03-20 10:54:42 +0000 |
|---|---|---|
| committer | Sudakshina Das <sudi@gcc.gnu.org> | 2018-03-20 10:54:42 +0000 |
| commit | 094daefb7b79201ee5b39b07a64f9947524e6b2d (patch) | |
| tree | ad88df4dad7de2ec94ab8b527e66d64c52e57485 /gcc/config/arm/neon.md | |
| parent | 038012e2d9211e56a2d6710a85314373af9d4d44 (diff) | |
| download | gcc-094daefb7b79201ee5b39b07a64f9947524e6b2d.zip gcc-094daefb7b79201ee5b39b07a64f9947524e6b2d.tar.gz gcc-094daefb7b79201ee5b39b07a64f9947524e6b2d.tar.bz2 | |
[ARM][PR82989] Fix unexpected use of NEON instructions for shifts
This patch fixes PR82989 so that we avoid NEON instructions when
-mneon-for-64bits is not enabled. This is more of a short term fix
for the real deeper problem of making an early decision of choosing
or rejecting NEON instructions. There is now a new ticket PR84467 to
deal with the longer term solution.
(Please refer to the discussion in the bug report for more details).
Sudi
*** gcc/ChangeLog ***
2018-03-20 Sudakshina Das <sudi.das@arm.com>
PR target/82989
* config/arm/neon.md (ashldi3_neon): Update ?s for constraints
to favor GPR over NEON registers.
(<shift>di3_neon): Likewise.
*** gcc/testsuite/ChangeLog ***
2018-03-20 Sudakshina Das <sudi.das@arm.com>
PR target/82989
* gcc.target/arm/pr82989.c: New test.
From-SVN: r258677
Diffstat (limited to 'gcc/config/arm/neon.md')
| -rw-r--r-- | gcc/config/arm/neon.md | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 6a6f5d7..1646b21 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -1180,12 +1180,12 @@ ) (define_insn_and_split "ashldi3_neon" - [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?&r, ?w,w") - (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0, r, 0w,w") - (match_operand:SI 2 "general_operand" "rUm, i, r, i, i,rUm,i"))) - (clobber (match_scratch:SI 3 "= X, X,?&r, X, X, X,X")) - (clobber (match_scratch:SI 4 "= X, X,?&r, X, X, X,X")) - (clobber (match_scratch:DI 5 "=&w, X, X, X, X, &w,X")) + [(set (match_operand:DI 0 "s_register_operand" "= w, w, &r, r, &r, ?w,?w") + (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0, r, 0w, w") + (match_operand:SI 2 "general_operand" "rUm, i, r, i, i,rUm, i"))) + (clobber (match_scratch:SI 3 "= X, X, &r, X, X, X, X")) + (clobber (match_scratch:SI 4 "= X, X, &r, X, X, X, X")) + (clobber (match_scratch:DI 5 "=&w, X, X, X, X, &w, X")) (clobber (reg:CC_C CC_REGNUM))] "TARGET_NEON" "#" @@ -1276,7 +1276,7 @@ ;; ashrdi3_neon ;; lshrdi3_neon (define_insn_and_split "<shift>di3_neon" - [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?&r,?w,?w") + [(set (match_operand:DI 0 "s_register_operand" "= w, w, &r, r, &r,?w,?w") (RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0, r,0w, w") (match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, i, r, i"))) (clobber (match_scratch:SI 3 "=2r, X, &r, X, X,2r, X")) |