arm&aarch64: subdivide the type attribute "alu_shfit_imm"

The type attribute "alu_shfit_imm" is subdivided into
"alu_shift_imm_lsl_1to4" and "alu_shift_imm_other", to accommodate
optimazations of some microarchitectures.

Here is the detailed discussion.
https://gcc.gnu.org/pipermail/gcc/2020-September/233594.html

gcc/
	* config/arm/types.md (define_attr "autodetect_type"): New.
	(define_attr "type"): Subdivide alu_shift_imm.
	* config/arm/common.md: New file.
	* config/aarch64/predicates.md:Include common.md.
	* config/arm/predicates.md:Include common.md.
	* config/aarch64/aarch64.md (*add_<shift>_<mode>): Set autodetect_type.
	(*add_<shift>_si_uxtw): Likewise.
	(*sub_<shift>_<mode>): Likewise.
	(*sub_<shift>_si_uxtw): Likewise.
	(*neg_<shift>_<mode>2): Likewise.
	(*neg_<shift>_si2_uxtw): Likewise.
	* config/arm/arm.md (*addsi3_carryin_shift): Likewise.
	(add_not_shift_cin): Likewise.
	(*subsi3_carryin_shift): Likewise.
	(*subsi3_carryin_shift_alt): Likewise.
	(*rsbsi3_carryin_shift): Likewise.
	(*rsbsi3_carryin_shift_alt): Likewise.
	(*arm_shiftsi3): Likewise.
	(*<arith_shift_insn>_multsi): Likewise.
	(*<arith_shift_insn>_shiftsi): Likewise.
	(subsi3_carryin): Set new type.
	(*if_arith_move): Set new type.
	(*if_move_arith): Set new type.
	(define_attr "core_cycles"): Use new type.
	* config/arm/arm-fixed.md (arm_ssatsihi_shift): Set autodetect_type.
	* config/arm/thumb2.md (*orsi_not_shiftsi_si): Likewise.
	(*thumb2_shiftsi3_short): Set new type.
	* config/aarch64/falkor.md (falkor_alu_1_xyz): Use new type.
	* config/aarch64/saphira.md (saphira_alu_1_xyz): Likewise.
	* config/aarch64/thunderx.md (thunderx_arith_shift): Likewise.
	* config/aarch64/thunderx2t99.md (thunderx2t99_alu_shift): Likewise.
	* config/aarch64/thunderx3t110.md (thunderx3t110_alu_shift): Likewise.
	(thunderx3t110_alu_shift1): Likewise.
	* config/aarch64/tsv110.md (tsv110_alu_shift): Likewise.
	* config/arm/arm1020e.md (1020alu_shift_op): Likewise.
	* config/arm/arm1026ejs.md (alu_shift_op): Likewise.
	* config/arm/arm1136jfs.md (11_alu_shift_op): Likewise.
	* config/arm/arm926ejs.md (9_alu_op): Likewise.
	* config/arm/cortex-a15.md (cortex_a15_alu_shift): Likewise.
	* config/arm/cortex-a17.md (cortex_a17_alu_shiftimm): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_alu_shift): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a57.md (cortex_a57_alu_shift): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_alu_shift): Likewise.
	* config/arm/cortex-a8.md (cortex_a8_alu_shift): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_dp_shift): Likewise.
	* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
	* config/arm/cortex-m7.md (cortex_m7_alu_shift): Likewise.
	* config/arm/cortex-r4.md (cortex_r4_alu_shift): Likewise.
	* config/arm/exynos-m1.md (exynos_m1_alu_shift): Likewise.
	* config/arm/fa526.md (526_alu_shift_op): Likewise.
	* config/arm/fa606te.md (606te_alu_op): Likewise.
	* config/arm/fa626te.md (626te_alu_shift_op): Likewise.
	* config/arm/fa726te.md (726te_alu_shift_op): Likewise.
	* config/arm/fmp626.md (mp626_alu_shift_op): Likewise.
	* config/arm/marvell-pj4.md (pj4_shift): Likewise.
	(pj4_shift_conds): Likewise.
	(pj4_alu_shift): Likewise.
	(pj4_alu_shift_conds): Likewise.
	* config/arm/xgene1.md (xgene1_alu): Likewise.
	* config/arm/arm.c (xscale_sched_adjust_cost): Likewise.

1 files changed, 18 insertions, 13 deletions

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 1a8e498..13b09c3 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -336,7 +336,8 @@
 (define_attr "core_cycles" "single,multi"
   (if_then_else (eq_attr "type"
     "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\
-    alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\
+    alu_shift_imm_lsl_1to4, alu_shift_imm_other, alu_shift_reg, alu_dsp_reg,\
+    alus_ext, alus_imm, alus_sreg,\
     alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
     logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
     logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
@@ -1370,7 +1371,7 @@
    (set_attr "arch" "32,a")
    (set_attr "shift" "3")
    (set_attr "predicable" "yes")
-   (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+   (set_attr "autodetect_type" "alu_shift_operator2")] 
 )
 
 (define_insn "*addsi3_carryin_clobercc"
@@ -1679,7 +1680,7 @@
   [(set_attr "conds" "use")
    (set_attr "arch" "*,a,t2")
    (set_attr "predicable" "yes")
-   (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")]
+   (set_attr "type" "adc_reg,adc_imm,alu_shift_imm_lsl_1to4")]
 )
 
 ;; Special canonicalization of the above when operand1 == (const_int 1):
@@ -1727,7 +1728,7 @@
   "rsc%?\\t%0, %4, %1%S3"
   [(set_attr "conds" "use")
    (set_attr "predicable" "yes")
-   (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+   (set_attr "autodetect_type" "alu_shift_operator3")]
 )
 
 (define_insn "cmpsi3_carryin_<CC_EXTEND>out"
@@ -1811,7 +1812,7 @@
    (set_attr "arch" "32,a")
    (set_attr "shift" "3")
    (set_attr "predicable" "yes")
-   (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+   (set_attr "autodetect_type" "alu_shift_operator2")]
 )
 
 (define_insn "*subsi3_carryin_shift_alt"
@@ -1828,7 +1829,7 @@
    (set_attr "arch" "32,a")
    (set_attr "shift" "3")
    (set_attr "predicable" "yes")
-   (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+   (set_attr "autodetect_type" "alu_shift_operator2")]
 )
 
 ;; No RSC in Thumb2
@@ -1844,7 +1845,7 @@
   "rsc%?\\t%0, %1, %3%S2"
   [(set_attr "conds" "use")
    (set_attr "predicable" "yes")
-   (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+   (set_attr "autodetect_type" "alu_shift_operator2")]
 )
 
 (define_insn "*rsbsi3_carryin_shift_alt"
@@ -1859,7 +1860,7 @@
   "rsc%?\\t%0, %1, %3%S2"
   [(set_attr "conds" "use")
    (set_attr "predicable" "yes")
-   (set_attr "type" "alu_shift_imm,alu_shift_reg")]
+   (set_attr "autodetect_type" "alu_shift_operator2")]
 )
 
 ; transform ((x << y) - 1) to ~(~(x-1) << y)  Where X is a constant.
@@ -4646,7 +4647,7 @@
    (set_attr "predicable_short_it" "yes,yes,no,no")
    (set_attr "length" "4")
    (set_attr "shift" "1")
-   (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_imm,alu_shift_reg")]
+   (set_attr "autodetect_type" "alu_shift_operator3")]
 )
 
 (define_insn "*shiftsi3_compare0"
@@ -9503,7 +9504,7 @@
   [(set_attr "predicable" "yes")
    (set_attr "shift" "2")
    (set_attr "arch" "a,t2")
-   (set_attr "type" "alu_shift_imm")])
+   (set_attr "autodetect_type" "alu_shift_mul_op3")])
 
 (define_insn "*<arith_shift_insn>_shiftsi"
   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
@@ -9517,7 +9518,7 @@
   [(set_attr "predicable" "yes")
    (set_attr "shift" "3")
    (set_attr "arch" "a,t2,a")
-   (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_reg")])
+   (set_attr "autodetect_type" "alu_shift_operator2")])
 
 (define_split
   [(set (match_operand:SI 0 "s_register_operand" "")
@@ -10856,7 +10857,9 @@
    (set_attr "length" "4,8")
    (set_attr_alternative "type"
                          [(if_then_else (match_operand 3 "const_int_operand" "")
-                                        (const_string "alu_shift_imm" )
+                                (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4")
+                                              (const_string "alu_shift_imm_lsl_1to4")
+                                              (const_string "alu_shift_imm_other"))
                                         (const_string "alu_shift_reg"))
                           (const_string "multiple")])]
 )
@@ -10921,7 +10924,9 @@
    (set_attr "length" "4,8")
    (set_attr_alternative "type"
                          [(if_then_else (match_operand 3 "const_int_operand" "")
-                                        (const_string "alu_shift_imm" )
+                                (if_then_else (match_operand 5 "alu_shift_operator_lsl_1_to_4")
+                                              (const_string "alu_shift_imm_lsl_1to4")
+                                              (const_string "alu_shift_imm_other"))
                                         (const_string "alu_shift_reg"))
                           (const_string "multiple")])]
 )