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authorRichard Earnshaw <rearnsha@arm.com>2005-04-09 12:03:54 +0000
committerRichard Earnshaw <rearnsha@gcc.gnu.org>2005-04-09 12:03:54 +0000
commitabac3b49c23d0c17ce227d4ae69d2fbd30535d5a (patch)
tree22815b80db64c76f5385a4035863b0bd38a6fa6e /gcc/config/arm/arm.c
parent835d64ab880ab3932c0e67c87ff859472771456d (diff)
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arm.c (FL_WBUF): Define.
* arm.c (FL_WBUF): Define. (arm_tune_strongarm): Renamed from arm_is_strong. All uses changed. (arm_is_6_or_7): Delete. (arm_tune_wbuf): New. (arm_override_options): Set arm_tune_wbuf. * arm.h (arm_tune_strongarm): Renamed from arm_is_strong. (arm_is_6_or_7): Delete declaration. (arm_tune_wbuf): New declartion. * arm.md (is_strongarm): Derive from arm_tune_strongarm. (model_wbuf): Derive from arm_tune_wbuf. * arm-cores.def (arm600, arm610, arm620, arm700, arm700i, arm710) (arm720, arm710c, arm7100, arm7500, arm7500fe, arm710t, arm720t) (arm740t): Mark CPUs as having a write buffer. From-SVN: r97894
Diffstat (limited to 'gcc/config/arm/arm.c')
-rw-r--r--gcc/config/arm/arm.c18
1 files changed, 10 insertions, 8 deletions
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a1abe96..13cf323 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -386,6 +386,8 @@ static int thumb_call_reg_needed;
#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
+#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
+ Note: ARM6 & 7 derivatives only. */
#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
@@ -438,7 +440,7 @@ int arm_arch6 = 0;
int arm_ld_sched = 0;
/* Nonzero if this chip is a StrongARM. */
-int arm_is_strong = 0;
+int arm_tune_strongarm = 0;
/* Nonzero if this chip is a Cirrus variant. */
int arm_arch_cirrus = 0;
@@ -452,8 +454,9 @@ int arm_arch_xscale = 0;
/* Nonzero if tuning for XScale */
int arm_tune_xscale = 0;
-/* Nonzero if this chip is an ARM6 or an ARM7. */
-int arm_is_6_or_7 = 0;
+/* Nonzero if we want to tune for stores that access the write-buffer.
+ This typicallly means an ARM6 or ARM7 with MMU or MPU. */
+int arm_tune_wbuf = 0;
/* Nonzero if generating Thumb instructions. */
int thumb_code = 0;
@@ -980,10 +983,9 @@ arm_override_options (void)
arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
- arm_is_strong = (tune_flags & FL_STRONG) != 0;
+ arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
thumb_code = (TARGET_ARM == 0);
- arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
- && !(tune_flags & FL_ARCH4))) != 0;
+ arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
@@ -1182,7 +1184,7 @@ arm_override_options (void)
/* StrongARM has early execution of branches, so a sequence
that is worth skipping is shorter. */
- if (arm_is_strong)
+ if (arm_tune_strongarm)
max_insns_skipped = 3;
}
@@ -1396,7 +1398,7 @@ use_return_insn (int iscond, rtx sibling)
/* On StrongARM, conditional returns are expensive if they aren't
taken and multiple registers have been stacked. */
- if (iscond && arm_is_strong)
+ if (iscond && arm_tune_strongarm)
{
/* Conditional return when just the LR is stored is a simple
conditional-load instruction, that's not expensive. */