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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2021-06-09 12:12:57 +0300 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2021-06-09 12:12:57 +0300 |
| commit | c0ba7a8af5366c37241f20e8be41e362f7260389 (patch) | |
| tree | 6dff994f3ed1329cab83f5b4a77c8cfbb0e2de97 /gcc/config/arc/arc.c | |
| parent | d4d38135b3137f1d3148138340e67bdcd7ea8216 (diff) | |
| download | gcc-c0ba7a8af5366c37241f20e8be41e362f7260389.zip gcc-c0ba7a8af5366c37241f20e8be41e362f7260389.tar.gz gcc-c0ba7a8af5366c37241f20e8be41e362f7260389.tar.bz2 | |
arc: Update 64bit move split patterns.
ARCv2HS can use a limited number of instructions to implement 64bit
moves. The VADD2 is used as a 64bit move, the LDD/STD are 64 bit loads
and stores. All those instructions are not baseline, hence we need to
provide alternatives when they are not available or cannot be generate
due to instruction restriction.
This patch is cleaning up those move patterns, and updates splits
instruction lengths.
gcc/
2021-06-09 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-protos.h (arc_split_move_p): New prototype.
* config/arc/arc.c (arc_split_move_p): New function.
(arc_split_move): Clean up.
* config/arc/arc.md (movdi_insn): Clean up, use arc_split_move_p.
(movdf_insn): Likewise.
* config/arc/simdext.md (mov<VWH>_insn): Likewise.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Diffstat (limited to 'gcc/config/arc/arc.c')
| -rw-r--r-- | gcc/config/arc/arc.c | 44 |
1 files changed, 25 insertions, 19 deletions
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 0d34c96..69f6ae4 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -10108,6 +10108,31 @@ arc_process_double_reg_moves (rtx *operands) return true; } + +/* Check if we need to split a 64bit move. We do not need to split it if we can + use vadd2 or ldd/std instructions. */ + +bool +arc_split_move_p (rtx *operands) +{ + machine_mode mode = GET_MODE (operands[0]); + + if (TARGET_LL64 + && ((memory_operand (operands[0], mode) + && (even_register_operand (operands[1], mode) + || satisfies_constraint_Cm3 (operands[1]))) + || (memory_operand (operands[1], mode) + && even_register_operand (operands[0], mode)))) + return false; + + if (TARGET_PLUS_QMACW + && even_register_operand (operands[0], mode) + && even_register_operand (operands[1], mode)) + return false; + + return true; +} + /* operands 0..1 are the operands of a 64 bit move instruction. split it into two moves with operands 2/3 and 4/5. */ @@ -10125,25 +10150,6 @@ arc_split_move (rtx *operands) return; } - if (TARGET_LL64 - && ((memory_operand (operands[0], mode) - && (even_register_operand (operands[1], mode) - || satisfies_constraint_Cm3 (operands[1]))) - || (memory_operand (operands[1], mode) - && even_register_operand (operands[0], mode)))) - { - emit_move_insn (operands[0], operands[1]); - return; - } - - if (TARGET_PLUS_QMACW - && even_register_operand (operands[0], mode) - && even_register_operand (operands[1], mode)) - { - emit_move_insn (operands[0], operands[1]); - return; - } - if (TARGET_PLUS_QMACW && GET_CODE (operands[1]) == CONST_VECTOR) { |