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| author | Richard Henderson <rth@redhat.com> | 2005-04-18 09:13:00 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2005-04-18 09:13:00 -0700 |
| commit | 0b196b187b335a83b98c9dcad22b75ba84c455b9 (patch) | |
| tree | d03d3c5e67f21af4ac017cf55ce23f1beda9b168 /gcc/config/alpha/ev5.md | |
| parent | 46c94db61830d164a410f0f09d605c9cecedb2eb (diff) | |
| download | gcc-0b196b187b335a83b98c9dcad22b75ba84c455b9.zip gcc-0b196b187b335a83b98c9dcad22b75ba84c455b9.tar.gz gcc-0b196b187b335a83b98c9dcad22b75ba84c455b9.tar.bz2 | |
alpha.c (alpha_split_atomic_op): New.
* config/alpha/alpha.c (alpha_split_atomic_op): New.
(alphaev5_insn_pipe): Add LD_L, ST_C, MB types.
(alphaev4_insn_pipe): Likewise. Correct IST and LDSYM pipes.
* config/alpha/alpha-protos.h: Update.
* config/alpha/alpha.md (UNSPECV_MB, UNSPECV_LL, UNSPECV_SC): New.
(UNSPECV_ATOMIC, UNSPECV_CMPXCHG, UNSPECV_XCHG): New.
(attr type): Add ld_l, st_c, mb.
(andsi_internal, andnotsi3, iorsi_internal, one_cmplsi_internal,
iornotsi3, xorsi_internal, xornotsi3): New.
* config/alpha/ev4.md (ev4_ld): Add ld_l.
(ev4_ist_c, ev4_mb): New.
* config/alpha/ev5.md (ev5_st): Add st_c, mb.
(ev5_ld_l): New.
* config/alpha/ev6.md (ev6_ild): Add ld_l.
(ev6_ist): Add st_c.
(ev6_mb): New.
* config/alpha/sync.md: New file.
From-SVN: r98328
Diffstat (limited to 'gcc/config/alpha/ev5.md')
| -rw-r--r-- | gcc/config/alpha/ev5.md | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/gcc/config/alpha/ev5.md b/gcc/config/alpha/ev5.md index d4b0b95..b61cfe8 100644 --- a/gcc/config/alpha/ev5.md +++ b/gcc/config/alpha/ev5.md @@ -43,7 +43,7 @@ (define_insn_reservation "ev5_st" 1 (and (eq_attr "tune" "ev5") - (eq_attr "type" "ist,fst")) + (eq_attr "type" "ist,fst,st_c,mb")) "ev5_e0+ev5_st") ; Loads from L0 complete in two cycles. adjust_cost still factors @@ -53,6 +53,11 @@ (eq_attr "type" "ild,fld,ldsym")) "ev5_e01+ev5_ld") +(define_insn_reservation "ev5_ld_l" 1 + (and (eq_attr "tune" "ev5") + (eq_attr "type" "ld_l")) + "ev5_e0+ev5_ld") + ; Integer branches slot only to E1. (define_insn_reservation "ev5_ibr" 1 (and (eq_attr "tune" "ev5") @@ -129,7 +134,7 @@ ; Model this instead with increased latency on the input instruction. (define_bypass 3 - "ev5_ld,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp" + "ev5_ld,ev5_ld_l,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp" "ev5_imull,ev5_imulq,ev5_imulh") (define_bypass 9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh") |