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| author | Uros Bizjak <ubizjak@gmail.com> | 2015-05-12 22:05:23 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2015-05-12 22:05:23 +0200 |
| commit | f06ed65044c0cba7f9cb8d6d8a8b99ee81953e4e (patch) | |
| tree | 68c26a1c4dff0c873ce58f57d20a529df940f53c /gcc/config/alpha/alpha.md | |
| parent | 46b35980b831a980f762753b64c83e1ab8eac880 (diff) | |
| download | gcc-f06ed65044c0cba7f9cb8d6d8a8b99ee81953e4e.zip gcc-f06ed65044c0cba7f9cb8d6d8a8b99ee81953e4e.tar.gz gcc-f06ed65044c0cba7f9cb8d6d8a8b99ee81953e4e.tar.bz2 | |
alpha.h (TARGET_SUPPORTS_WIDE_INT): New define.
* config/alpha/alpha.h (TARGET_SUPPORTS_WIDE_INT): New define.
* config/alpha/alpha.c (alpha_rtx_costs): Handle CONST_WIDE_INT.
(alpha_extract_integer): Ditto.
(alpha_legitimate_constant_p): Ditto.
(alpha_split_tmode_pair): Ditto.
(alpha_preferred_reload_class): Add CONST_WIDE_INT.
(alpha_expand_mov): Ditto.
(print_operand): Remove handling of 'H' modifier.
<case 'm'>: Remove CONST_DOUBLE handling.
(summarize_insn): Handle CONST_WIDE_INT.
* config/alpha/alpha.md (*andsi_internal): Remove H constraint.
(anddi3): Ditto.
(movti): Handle CONST_WIDE_INT.
* config/alpha/constraints.md ('H'): Remove constraint definition.
('G'): Do not match MODE_FLOAT class.
* config/alpha/predicates.md (const0_operand): Also match
const_wide_int.
(non_add_const_operand): Ditto.
(non_zero_const_operand): Ditto.
(some_operand): Ditto.
(input_operand): Ditto. Handle CONST_WIDE_INT.
(and_operand): Do not match const_double.
* config/alpha/sync.md (fetchop_constr): Remove H constraint.
From-SVN: r223097
Diffstat (limited to 'gcc/config/alpha/alpha.md')
| -rw-r--r-- | gcc/config/alpha/alpha.md | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index eb59f6c..2323de9 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -922,7 +922,7 @@ (define_insn "*andsi_internal" [(set (match_operand:SI 0 "register_operand" "=r,r,r") (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ") - (match_operand:SI 2 "and_operand" "rI,N,MH")))] + (match_operand:SI 2 "and_operand" "rI,N,M")))] "" "@ and %r1,%2,%0 @@ -933,7 +933,7 @@ (define_insn "anddi3" [(set (match_operand:DI 0 "register_operand" "=r,r,r") (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") - (match_operand:DI 2 "and_operand" "rI,N,MH")))] + (match_operand:DI 2 "and_operand" "rI,N,M")))] "" "@ and %r1,%2,%0 @@ -4154,6 +4154,7 @@ 32-bit constants in TImode and rely on the splitter, but this doesn't seem to be worth the pain. */ else if (CONST_INT_P (operands[1]) + || GET_CODE (operands[1]) == CONST_WIDE_INT || GET_CODE (operands[1]) == CONST_DOUBLE) { rtx in[2], out[2], target; |