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authorRichard Sandiford <richard.sandiford@arm.com>2019-09-17 17:00:58 +0000
committerRichard Sandiford <rsandifo@gcc.gnu.org>2019-09-17 17:00:58 +0000
commitf62281dc1b3d751977266d8c30b4488833fcb9dd (patch)
treee9e12be32b1c09ea846e54abb2e6168375fdc862 /gcc/config/aarch64
parent5d4efa795e09a17e1773e8862db8f55aa7fe90c5 (diff)
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[arm][aarch64] Make no_insn issue to nothing
no_insn is documented as: an insn which does not represent an instruction in the final output, thus having no impact on scheduling. and is used in that way by the arm port (e.g. for define_insns that expand to comments). However, most scheduling descriptions instead assigned units to no_insn patterns, in some cases treating them as more expensive than a plain move. This patch removes the no_insn handling from individual scheduling descriptions and uses a common define_insn_reservation for all CPUs. 2019-09-17 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/arm/types.md (no_reservation): New reservation. * config/aarch64/falkor.md (falkor_other_0_nothing): Don't handle no_insn here. * config/aarch64/saphira.md (saphira_other_0_nothing): Likewise. * config/aarch64/thunderx2t99.md (thunderx2t99_nothing): Likewise. * config/aarch64/tsv110.md (tsv110_alu): Likewise. * config/arm/arm1020e.md (1020alu_op): Likewise. * config/arm/arm1026ejs.md (alu_op): Likewise. * config/arm/arm1136jfs.md (11_alu_op): Likewise. * config/arm/arm926ejs.md (9_alu_op): Likewise. * config/arm/cortex-a15.md (cortex_a15_alu): Likewise. * config/arm/cortex-a17.md (cortex_a17_alu): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu): Likewise. * config/arm/cortex-a53.md (cortex_a53_alu): Likewise. * config/arm/cortex-a57.md (cortex_a57_alu): Likewise. * config/arm/cortex-a7.md (cortex_a7_alu_shift): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. * config/arm/cortex-m7.md (cortex_m7_alu_simple): Likewise. * config/arm/cortex-r4.md (cortex_r4_alu_shift_reg): Likewise. * config/arm/fa526.md (526_alu_op): Likewise. * config/arm/fa606te.md (606te_alu_op): Likewise. * config/arm/fa626te.md (626te_alu_op): Likewise. * config/arm/fa726te.md (726te_alu_op): Likewise. * config/arm/xgene1.md (xgene1_nop): Likewise. From-SVN: r275807
Diffstat (limited to 'gcc/config/aarch64')
-rw-r--r--gcc/config/aarch64/falkor.md2
-rw-r--r--gcc/config/aarch64/saphira.md2
-rw-r--r--gcc/config/aarch64/thunderx2t99.md2
-rw-r--r--gcc/config/aarch64/tsv110.md2
4 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/aarch64/falkor.md b/gcc/config/aarch64/falkor.md
index 41955af..2bcc661 100644
--- a/gcc/config/aarch64/falkor.md
+++ b/gcc/config/aarch64/falkor.md
@@ -648,7 +648,7 @@
(define_insn_reservation "falkor_other_0_nothing" 0
(and (eq_attr "tune" "falkor")
- (eq_attr "type" "no_insn,trap,block"))
+ (eq_attr "type" "trap,block"))
"nothing")
(define_insn_reservation "falkor_other_2_z" 2
diff --git a/gcc/config/aarch64/saphira.md b/gcc/config/aarch64/saphira.md
index 853deee..3cc7bc4 100644
--- a/gcc/config/aarch64/saphira.md
+++ b/gcc/config/aarch64/saphira.md
@@ -520,7 +520,7 @@
(define_insn_reservation "saphira_other_0_nothing" 0
(and (eq_attr "tune" "saphira")
- (eq_attr "type" "no_insn,trap,block"))
+ (eq_attr "type" "trap,block"))
"nothing")
(define_insn_reservation "saphira_other_2_ld" 2
diff --git a/gcc/config/aarch64/thunderx2t99.md b/gcc/config/aarch64/thunderx2t99.md
index c43c39e..bb6e0ab 100644
--- a/gcc/config/aarch64/thunderx2t99.md
+++ b/gcc/config/aarch64/thunderx2t99.md
@@ -74,7 +74,7 @@
(define_insn_reservation "thunderx2t99_nothing" 0
(and (eq_attr "tune" "thunderx2t99")
- (eq_attr "type" "no_insn,block"))
+ (eq_attr "type" "block"))
"nothing")
(define_insn_reservation "thunderx2t99_mrs" 0
diff --git a/gcc/config/aarch64/tsv110.md b/gcc/config/aarch64/tsv110.md
index 680c48a..f20055d 100644
--- a/gcc/config/aarch64/tsv110.md
+++ b/gcc/config/aarch64/tsv110.md
@@ -281,7 +281,7 @@
shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
- mrs,multiple,no_insn"))
+ mrs,multiple"))
"tsv110_alu1|tsv110_alu2|tsv110_alu3")
(define_insn_reservation "tsv110_alus" 1