diff options
| author | Yuliang Wang <yuliang.wang@arm.com> | 2019-09-27 08:10:30 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-09-27 08:10:30 +0000 |
| commit | 76bb5af63db66ccaee0f0ae59783eda972d0db83 (patch) | |
| tree | d3246691a2f325d294fd92c5d30f53aef86ae7c3 /gcc/config/aarch64 | |
| parent | 639a28ba6e0e5807ae062475f35cc6895e32ef17 (diff) | |
| download | gcc-76bb5af63db66ccaee0f0ae59783eda972d0db83.zip gcc-76bb5af63db66ccaee0f0ae59783eda972d0db83.tar.gz gcc-76bb5af63db66ccaee0f0ae59783eda972d0db83.tar.bz2 | |
[AArch64][SVE2] Shift-Right Accumulate combine patterns
This patch adds combining support for SVE2's shift-right accumulate
instructions.
2019-09-27 Yuliang Wang <yuliang.wang@arm.com>
gcc/
* config/aarch64/aarch64-sve2.md (aarch64_sve2_sra<mode>):
New combine pattern.
gcc/testsuite/
* gcc.target/aarch64/sve2/shracc_1.c: New test.
From-SVN: r276174
Diffstat (limited to 'gcc/config/aarch64')
| -rw-r--r-- | gcc/config/aarch64/aarch64-sve2.md | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index ee9acdc..b018f5b 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -123,3 +123,22 @@ } ) +;; Unpredicated signed / unsigned shift-right accumulate. +(define_insn_and_rewrite "*aarch64_sve2_sra<mode>" + [(set (match_operand:SVE_I 0 "register_operand" "=w") + (plus:SVE_I + (unspec:SVE_I + [(match_operand 4) + (SHIFTRT:SVE_I + (match_operand:SVE_I 2 "register_operand" "w") + (match_operand:SVE_I 3 "aarch64_simd_rshift_imm" "Dr"))] + UNSPEC_PRED_X) + (match_operand:SVE_I 1 "register_operand" "0")))] + "TARGET_SVE2" + "<sra_op>sra\t%0.<Vetype>, %2.<Vetype>, #%3" + "&& !CONSTANT_P (operands[4])" + { + operands[4] = CONSTM1_RTX (<VPRED>mode); + } +) + |