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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2018-09-19 10:24:59 +0000 |
|---|---|---|
| committer | Matthew Malcomson <matmal01@gcc.gnu.org> | 2018-09-19 10:24:59 +0000 |
| commit | 3c5af60836eed835b818f2a87480155a497139a4 (patch) | |
| tree | cc5018970428d8d38fd290cd73f0120a24a26046 /gcc/config/aarch64/constraints.md | |
| parent | 574f5885f7d0fce6cb7f3b0bcf476871722d0bc9 (diff) | |
| download | gcc-3c5af60836eed835b818f2a87480155a497139a4.zip gcc-3c5af60836eed835b818f2a87480155a497139a4.tar.gz gcc-3c5af60836eed835b818f2a87480155a497139a4.tar.bz2 | |
[AARCH64] Use STLUR for atomic_store
Use the STLUR instruction introduced in Armv8.4-a.
This instruction has the store-release semantic like STLR but can take a
9-bit unscaled signed immediate offset.
Example test case:
```
void
foo ()
{
int32_t *atomic_vals = calloc (4, sizeof (int32_t));
atomic_store_explicit (atomic_vals + 1, 2, memory_order_release);
}
```
Before patch generates
```
foo:
stp x29, x30, [sp, -16]!
mov x1, 4
mov x0, x1
mov x29, sp
bl calloc
mov w1, 2
add x0, x0, 4
stlr w1, [x0]
ldp x29, x30, [sp], 16
ret
```
After patch generates
```
foo:
stp x29, x30, [sp, -16]!
mov x1, 4
mov x0, x1
mov x29, sp
bl calloc
mov w1, 2
stlur w1, [x0, 4]
ldp x29, x30, [sp], 16
ret
```
We introduce a new feature flag to indicate the presence of this instruction.
The feature flag is called AARCH64_ISA_RCPC8_4 and is included when targeting
armv8.4 architecture.
We also introduce an "arch" attribute to be checked called "rcpc8_4" after this
feature flag.
gcc/
2018-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
* config/aarch64/aarch64-protos.h
(aarch64_offset_9bit_signed_unscaled_p): New declaration.
* config/aarch64/aarch64.md (arches): New "rcpc8_4" attribute value.
(arch_enabled): Add check for "rcpc8_4" attribute value of "arch".
* config/aarch64/aarch64.h (AARCH64_FL_RCPC8_4): New bitfield.
(AARCH64_FL_FOR_ARCH8_4): Include AARCH64_FL_RCPC8_4.
(AARCH64_FL_PROFILE): Move index so flags are ordered.
(AARCH64_ISA_RCPC8_4): New flag.
* config/aarch64/aarch64.c (offset_9bit_signed_unscaled_p): Renamed
to aarch64_offset_9bit_signed_unscaled_p.
* config/aarch64/atomics.md (atomic_store<mode>): Allow offset
and use stlur.
* config/aarch64/constraints.md (Ust): New constraint.
* config/aarch64/predicates.md.
(aarch64_9bit_offset_memory_operand): New predicate.
(aarch64_rcpc_memory_operand): New predicate.
gcc/testsuite/
2018-09-19 Matthew Malcomson <matthew.malcomson@arm.com>
* gcc.target/aarch64/atomic-store.c: New.
From-SVN: r264421
Diffstat (limited to 'gcc/config/aarch64/constraints.md')
| -rw-r--r-- | gcc/config/aarch64/constraints.md | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 31fc3ea..99dac3b 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -225,6 +225,11 @@ (and (match_code "mem") (match_test "REG_P (XEXP (op, 0))"))) +(define_memory_constraint "Ust" + "@internal + A memory address with 9bit unscaled offset." + (match_operand 0 "aarch64_9bit_offset_memory_operand")) + (define_memory_constraint "Ump" "@internal A memory address suitable for a load/store pair operation." |