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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2017-07-27 16:29:31 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2017-07-27 16:29:31 +0000 |
| commit | 2c2789d582f8fcafd9ef46a22dcb5ca08c5eecd8 (patch) | |
| tree | 2c0f09817f8455203b1c9380e0f904f72c8cfb9c /gcc/config.gcc | |
| parent | 06bd22f6099abe4fec73c988daf4cacd68f34329 (diff) | |
| download | gcc-2c2789d582f8fcafd9ef46a22dcb5ca08c5eecd8.zip gcc-2c2789d582f8fcafd9ef46a22dcb5ca08c5eecd8.tar.gz gcc-2c2789d582f8fcafd9ef46a22dcb5ca08c5eecd8.tar.bz2 | |
[PATCH][AArch64] Fix missing optimization for CMP+AND
During combine GCC tries to merge CMP (with zero) and AND into a TST. However,
in cases where an ANDS operand is not compatible, this was being missed. Adding
a define_split where this operand was moved to a register seems to help out.
Committed on behalf of Sudi Das
---
gcc/
2017-07-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64.md
(define_split for and<mode>3nr_compare): Move
non aarch64_logical_operand to a register.
(define_split for and_<SHIFT:optab><mode>3nr_compare0): Move non
register immediate operand to a register.
* config/aarch64/predicates.md (aarch64_mov_imm_operand): New.
gcc/testsuite
2017-07-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/tst_imm_split_1.c: New Test.
Co-Authored-By: Sudakshina Das <sudi.das@arm.com>
From-SVN: r250631
Diffstat (limited to 'gcc/config.gcc')
0 files changed, 0 insertions, 0 deletions