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| author | Jim Wilson <jimw@sifive.com> | 2018-07-06 03:14:47 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2018-07-05 20:14:47 -0700 |
| commit | edace3e2295db80d32b1a77676a3697c5029d71b (patch) | |
| tree | d778f16d39a5efdcb0d2d11038988fa94d98e559 /gcc/config.gcc | |
| parent | 90099a748f9ccc55ddffb86c503e7145e380d863 (diff) | |
| download | gcc-edace3e2295db80d32b1a77676a3697c5029d71b.zip gcc-edace3e2295db80d32b1a77676a3697c5029d71b.tar.gz gcc-edace3e2295db80d32b1a77676a3697c5029d71b.tar.bz2 | |
RISC-V: Add support for riscv-*-*.
* config.gcc (riscv*-*-*): When setting xlen, handle riscv-*.
From-SVN: r262463
Diffstat (limited to 'gcc/config.gcc')
| -rw-r--r-- | gcc/config.gcc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config.gcc b/gcc/config.gcc index 63162aa..78e84c2 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4091,7 +4091,7 @@ case "${target}" in supported_defaults="abi arch tune" case "${target}" in - riscv32*) xlen=32 ;; + riscv-* | riscv32*) xlen=32 ;; riscv64*) xlen=64 ;; *) echo "Unsupported RISC-V target ${target}" 1>&2; exit 1 ;; esac |