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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2017-02-06 21:07:37 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2017-02-06 21:07:37 +0000 |
| commit | 391675acd2d18d0b6e5130a4105cf66eb1664683 (patch) | |
| tree | d78a3445d015e0af4a13622f9fbbbdf7dd8c5568 /gcc/config.gcc | |
| parent | e495e31a20d8193166945c7417176da2535e6366 (diff) | |
| download | gcc-391675acd2d18d0b6e5130a4105cf66eb1664683.zip gcc-391675acd2d18d0b6e5130a4105cf66eb1664683.tar.gz gcc-391675acd2d18d0b6e5130a4105cf66eb1664683.tar.bz2 | |
re PR target/66144 (vector element operator produces very bad code)
[gcc]
2017-02-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/66144
* config/rs6000/vector.md (vcond<mode><mode>): Allow the true and
false values to be constant vectors with all 0 or all 1 bits set.
(vcondu<mode><mode>): Likewise.
* config/rs6000/predicates.md (vector_int_reg_or_same_bit): New
predicate.
(fpmask_comparison_operator): Update comment.
(vecint_comparison_operator): New predicate.
* config/rs6000/rs6000.c (rs6000_emit_vector_cond_expr): Optimize
vector conditionals when the true and false values are constant
vectors with all 0 bits or all 1 bits set.
[gcc/testsuite]
2017-02-06 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/66144
* gcc.target/powerpc/pr66144-1.c: New test.
* gcc.target/powerpc/pr66144-2.c: Likewise.
* gcc.target/powerpc/pr66144-3.c: Likewise.
From-SVN: r245222
Diffstat (limited to 'gcc/config.gcc')
0 files changed, 0 insertions, 0 deletions