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author | Kito Cheng <kito.cheng@gmail.com> | 2018-05-18 22:53:55 +0000 |
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committer | Jim Wilson <wilson@gcc.gnu.org> | 2018-05-18 15:53:55 -0700 |
commit | 09baee1ab152afb0466c00ce87f0d681f2a50e21 (patch) | |
tree | 099bc749227aa5e740a633ed64614b065584c3a2 /gcc/common | |
parent | dc2ebc998a679294a672ecb4f585d66c9f10f56e (diff) | |
download | gcc-09baee1ab152afb0466c00ce87f0d681f2a50e21.zip gcc-09baee1ab152afb0466c00ce87f0d681f2a50e21.tar.gz gcc-09baee1ab152afb0466c00ce87f0d681f2a50e21.tar.bz2 |
RISC-V: Add RV32E support.
Kito Cheng <kito.cheng@gmail.com>
Monk Chiang <sh.chiang04@gmail.com>
gcc/
* common/config/riscv/riscv-common.c (riscv_parse_arch_string):
Add support to parse rv32e*. Clear MASK_RVE for rv32i and rv64i.
* config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e.
* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define
__riscv_32e when TARGET_RVE. Handle ABI_ILP32E as soft-float ABI.
* config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E.
* config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE,
compute save_libcall_adjustment properly.
(riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E.
(riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E.
* config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E.
(STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE.
(GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise.
(ABI_SPEC): Handle mabi=ilp32e.
* config/riscv/riscv.opt (abi_type): Add ABI_ILP32E.
(RVE): Add RVE mask.
* doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info.
<-march>: Add rv32e as an example.
gcc/testsuite/
* gcc.dg/stack-usage-1.c: Add support for rv32e.
libgcc/
* config/riscv/save-restore.S: Add support for rv32e.
Co-Authored-By: Jim Wilson <jimw@sifive.com>
Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com>
From-SVN: r260384
Diffstat (limited to 'gcc/common')
-rw-r--r-- | gcc/common/config/riscv/riscv-common.c | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 9db8301..8a78aeb 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -27,7 +27,8 @@ along with GCC; see the file COPYING3. If not see #include "flags.h" #include "diagnostic-core.h" -/* Parse a RISC-V ISA string into an option mask. */ +/* Parse a RISC-V ISA string into an option mask. Must clear or set all arch + dependent mask bits, in case more than one -march string is passed. */ static void riscv_parse_arch_string (const char *isa, int *flags, location_t loc) @@ -48,6 +49,8 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc) { p++; + *flags &= ~MASK_RVE; + *flags |= MASK_MUL; *flags |= MASK_ATOMIC; *flags |= MASK_HARD_FLOAT; @@ -57,6 +60,8 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc) { p++; + *flags &= ~MASK_RVE; + *flags &= ~MASK_MUL; if (*p == 'm') *flags |= MASK_MUL, p++; @@ -77,6 +82,28 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc) } } } + else if (*p == 'e') + { + p++; + + *flags |= MASK_RVE; + + if (*flags & MASK_64BIT) + { + error ("RV64E is not a valid base ISA"); + return; + } + + *flags &= ~MASK_MUL; + if (*p == 'm') + *flags |= MASK_MUL, p++; + + *flags &= ~MASK_ATOMIC; + if (*p == 'a') + *flags |= MASK_ATOMIC, p++; + + *flags &= ~(MASK_HARD_FLOAT | MASK_DOUBLE_FLOAT); + } else { error_at (loc, "-march=%s: invalid ISA string", isa); |