Enable GCC support for AMX-TILE,AMX-INT8,AMX-BF16.

AMX-TILE:ldtilecfg/sttilecfg/tileloadd/tileloaddt1/tilezero/tilerelease
AMX-INT8:tdpbssd/tdpbsud/tdpbusd/tdpbuud
AMX-BF16:tdpbf16ps

gcc/ChangeLog

	* common/config/i386/i386-common.c (OPTION_MASK_ISA2_AMX_TILE_SET,
	OPTION_MASK_ISA2_AMX_INT8_SET, OPTION_MASK_ISA2_AMX_BF16_SET,
	OPTION_MASK_ISA2_AMX_TILE_UNSET, OPTION_MASK_ISA2_AMX_INT8_UNSET,
	OPTION_MASK_ISA2_AMX_BF16_UNSET, OPTION_MASK_ISA2_XSAVE_UNSET):
	New marcos.
	(ix86_handle_option): Hanlde -mamx-tile, -mamx-int8, -mamx-bf16.
	* common/config/i386/i386-cpuinfo.h (processor_types): Add
	FEATURE_AMX_TILE, FEATURE_AMX_INT8, FEATURE_AMX_BF16.
	* common/config/i386/cpuinfo.h (XSTATE_TILECFG,
	XSTATE_TILEDATA, XCR_AMX_ENABLED_MASK): New macro.
	(get_available_features): Enable AMX features only if
	their states are suoorited by OSXSAVE.
	* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY
	for amx-tile, amx-int8, amx-bf16.
	* config.gcc: Add amxtileintrin.h, amxint8intrin.h,
	amxbf16intrin.h to extra headers.
	* config/i386/amxbf16intrin.h: New file.
	* config/i386/amxint8intrin.h: Ditto.
	* config/i386/amxtileintrin.h: Ditto.
	* config/i386/cpuid.h (bit_AMX_BF16, bit_AMX_TILE, bit_AMX_INT8):
	New macro.
	* config/i386/i386-c.c (ix86_target_macros_internal): Define
	__AMX_TILE__, __AMX_INT8__, AMX_BF16__.
	* config/i386/i386-options.c (ix86_target_string): Add
	-mamx-tile, -mamx-int8, -mamx-bf16.
	(ix86_option_override_internal): Handle AMX-TILE,
	AMX-INT8, AMX-BF16.
	* config/i386/i386.h (TARGET_AMX_TILE, TARGET_AMX_TILE_P,
	TARGET_AMX_INT8, TARGET_AMX_INT8_P, TARGET_AMX_BF16_P,
	PTA_AMX_TILE, PTA_AMX_INT8, PTA_AMX_BF16): New macros.
	* config/i386/i386.opt: Add -mamx-tile, -mamx-int8, -mamx-bf16.
	* config/i386/immintrin.h: Include amxtileintrin.h,
	amxint8intrin.h, amxbf16intrin.h.
	* doc/invoke.texi: Document -mamx-tile, -mamx-int8, -mamx-bf16.
	* doc/extend.texi: Document amx-tile, amx-int8, amx-bf16.
	* doc/sourcebuild.texi ((Effective-Target Keywords, Other
	hardware attributes): Document amx_int8, amx_tile, amx_bf16.

gcc/testsuite/ChangeLog

	* lib/target-supports.exp (check_effective_target_amx_tile,
	check_effective_target_amx_int8,
	check_effective_target_amx_bf16): New proc.
	* g++.dg/other/i386-2.C: Add -mamx-tile, -mamx-int8, -mamx-bf16.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/sse-12.c: Ditto.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.
	* gcc.target/i386/funcspec-56.inc: Add new target attribute.
	* gcc.target/i386/amx-check.h: New header file.
	* gcc.target/i386/amxbf16-asmatt-1.c: New test.
	* gcc.target/i386/amxint8-asmatt-1.c: New test.
	* gcc.target/i386/amxtile-asmatt-1.c: Ditto.
	* gcc.target/i386/amxbf16-asmintel-1.c: Ditto.
	* gcc.target/i386/amxint8-asmintel-1.c: Ditto.
	* gcc.target/i386/amxtile-asmintel-1.c: Ditto.
	* gcc.target/i386/amxbf16-dpbf16ps-2.c: Ditto.
	* gcc.target/i386/amxint8-dpbssd-2.c: Ditto.
	* gcc.target/i386/amxint8-dpbsud-2.c: Ditto.
	* gcc.target/i386/amxint8-dpbusd-2.c: Ditto.
	* gcc.target/i386/amxint8-dpbuud-2.c: Ditto.
	* gcc.target/i386/amxtile-2.c: Ditto.

4 files changed, 72 insertions, 0 deletions

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 12237e2..c96455c 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -509,15 +509,20 @@ get_available_features (struct __processor_model *cpu_model,
 #define XSTATE_OPMASK			0x20
 #define XSTATE_ZMM			0x40
 #define XSTATE_HI_ZMM			0x80
+#define XSTATE_TILECFG			0x20000
+#define XSTATE_TILEDATA		0x40000
 
 #define XCR_AVX_ENABLED_MASK \
   (XSTATE_SSE | XSTATE_YMM)
 #define XCR_AVX512F_ENABLED_MASK \
   (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
+#define XCR_AMX_ENABLED_MASK \
+  (XSTATE_TILECFG | XSTATE_TILEDATA)
 
   /* Check if AVX and AVX512 are usable.  */
   int avx_usable = 0;
   int avx512_usable = 0;
+  int amx_usable = 0;
   if ((ecx & bit_OSXSAVE))
     {
       /* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and
@@ -533,6 +538,8 @@ get_available_features (struct __processor_model *cpu_model,
 	  avx512_usable = ((xcrlow & XCR_AVX512F_ENABLED_MASK)
 			   == XCR_AVX512F_ENABLED_MASK);
 	}
+      amx_usable = ((xcrlow & XCR_AMX_ENABLED_MASK)
+		    == XCR_AMX_ENABLED_MASK);
     }
 
 #define set_feature(f) \
@@ -651,6 +658,15 @@ get_available_features (struct __processor_model *cpu_model,
 	set_feature (FEATURE_PCONFIG);
       if (edx & bit_IBT)
 	set_feature (FEATURE_IBT);
+      if (amx_usable)
+	{
+	  if (edx & bit_AMX_TILE)
+	    set_feature (FEATURE_AMX_TILE);
+	  if (edx & bit_AMX_INT8)
+	    set_feature (FEATURE_AMX_INT8);
+	  if (edx & bit_AMX_BF16)
+	    set_feature (FEATURE_AMX_BF16);
+	}
       if (avx512_usable)
 	{
 	  if (ebx & bit_AVX512F)
diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 6e34095..1014214 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -101,6 +101,9 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
+#define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
+#define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8
+#define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16
 
 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
    as -msse4.2.  */
@@ -194,6 +197,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
    | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
    | OPTION_MASK_ISA_AVX_UNSET)
+#define OPTION_MASK_ISA2_XSAVE_UNSET OPTION_MASK_ISA2_AMX_TILE_UNSET
 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
 #define OPTION_MASK_ISA_AVX2_UNSET \
   (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
@@ -247,6 +251,9 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
 #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
+#define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE
+#define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
+#define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
    as -mno-sse4.1. */
@@ -931,6 +938,47 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       return true;
 
+    case OPT_mamx_tile:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
+	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
+	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
+	}
+      return true;
+
+    case OPT_mamx_int8:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
+	}
+      return true;
+
+    case OPT_mamx_bf16:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
+	}
+      return true;
+
     case OPT_mfma:
       if (value)
 	{
@@ -1265,6 +1313,8 @@ ix86_handle_option (struct gcc_options *opts,
 	{
 	  opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
 	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
 	}
       return true;
 
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index 84ca97e..5b94b1f 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -216,6 +216,9 @@ enum processor_features
   FEATURE_XSAVEC,
   FEATURE_XSAVEOPT,
   FEATURE_XSAVES,
+  FEATURE_AMX_TILE,
+  FEATURE_AMX_INT8,
+  FEATURE_AMX_BF16,
   CPU_FEATURE_MAX
 };
 
diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 08c9dbe..3c830ea 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -160,4 +160,7 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("xsaveopt", FEATURE_XSAVEOPT, P_NONE,
 			"-mxsaveopt")
   ISA_NAMES_TABLE_ENTRY("xsaves", FEATURE_XSAVES, P_NONE, "-mxsaves")
+  ISA_NAMES_TABLE_ENTRY("amx-tile", FEATURE_AMX_TILE, P_NONE, "-mamx-tile")
+  ISA_NAMES_TABLE_ENTRY("amx-int8", FEATURE_AMX_INT8, P_NONE, "-mamx-int8")
+  ISA_NAMES_TABLE_ENTRY("amx-bf16", FEATURE_AMX_BF16, P_NONE, "-mamx-bf16")
 ISA_NAMES_TABLE_END