Enable GCC support for AVX512_VP2INTERSECT which will be in tigerlaker.

There are two instructions for AVX512_VP2INTERSECT:
VP2INTERSECTD and VP2INTERSECTQ.

gcc/
2019-06-05  Hongtao Liu  <hongtao.liu@intel.com>

	* common/config/i386/i386-common.c
	(OPTION_MASK_ISA_AVX512VP2INTERSECT_SET,
	OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET): New macros.
	(OPTION_MASK_ISA2_AVX512F_UNSET): Add
	OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET.
	(ix86_handle_option): Handle -mavx512vp2intersect.
	* config/i386/avx512vp2intersectintrin.h: New.
	* config/i386/avx512vp2intersectvlintrin.h: New.
	* config/i386/cpuid.h (bit_AVX512VP2INTERSECT): New.
	* config/i386/driver-i386.c (host_detect_local_cpu): Detect
	AVX512VP2INTERSECT.
	* config/i386/i386-builtin-types.def: Add new types.
	* config/i386/i386-builtin.def: Add new builtins.
	* config/i386/i386-builtins.c: (enum processor_features): Add
	F_AVX512VP2INTERSECT.
	(static const _isa_names_table isa_names_table): Ditto.
	* config/i386/i386-c.c (ix86_target_macros_internal): Define
	__AVX512VP2INTERSECT__.
	* config/i386/i386-expand.c (ix86_expand_builtin): Expand
	IX86_BUILTIN_2INTERSECTD512, IX86_BUILTIN_2INTERSECTQ512,
	IX86_BUILTIN_2INTERSECTD256, IX86_BUILTIN_2INTERSECTQ256,
	IX86_BUILTIN_2INTERSECTD128, IX86_BUILTIN_2INTERSECTQ128.
	* config/i386/i386-modes.def (P2QI, P2HI): New modes.
	* config/i386/i386-options.c (ix86_target_string): Add
	-mavx512vp2intersect.
	(ix86_option_override_internal): Handle AVX512VP2INTERSECT.
	* config/i386/i386.c (ix86_hard_regno_nregs): Allocate two regs for
	P2HImode and P2QImode.
	(ix86_hard_regno_mode_ok): Register pair only starts at even hardreg
	number for P2QImode and P2HImode.
	(ix86_regmode_natural_size): New function.
	* config/i386/i386.h (TARGET_AVX512VP2INTERSECT,
	TARGET_AVX512VP2INTERSECT_P, PTA_AVX512VP2INTERSECT
	REGMODE_NATURAL_SIZE, MASK_PAIR_REGNO_P): New.
	* config/i386/i386-protos.h (ix86_regmode_natural_size): Declare
	* config/i386/i386.opt: Add -mavx512vp2intersect.
	* config/i386/immintrin.h: Include avx512vp2intersectintrin.h and
	avx512vp2intersectvlintrin.h.
	* config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_VP2INTERSECT.
	(define_mode_iterator VI48_AVX512VP2VL): New.
	(avx512vp2intersect_2intersect<mode>,
	avx512vp2intersect_2intersectv16si): New define_insn patterns.
	* config.gcc: Add avx512vp2intersectvlintrin.h and
	avx512vp2intersectintrin.h to extra_headers.
	* doc/invoke.texi: Document -mavx512vp2intersect.

gcc/testsuite
2019-06-06  Hongtao Liu  <hongtao.liu@intel.com>
	    Olga Makhotina  <olga.makhotina@intel.com>

	* gcc.target/i386/avx512-check.h: Handle bit_AVX512VP2INTERSECT.
	* gcc.target/i386/avx512vp2intersect-2intersect-1a.c: New test.
	* gcc.target/i386/avx512vp2intersect-2intersect-1b.c: Likewise.
	* gcc.target/i386/avx512vp2intersect-2intersectvl-1a.c: Likewise.
	* gcc.target/i386/avx512vp2intersect-2intersectvl-1b.c: Likewise.
	* gcc.target/i386/sse-12.c: Add -mavx512vp2intersect.
	* gcc.target/i386/sse-13.c: Likewsie.
	* gcc.target/i386/sse-14.c: Likewise.
	* gcc.target/i386/sse-22.c: Likewise.
	* gcc.target/i386/sse-23.c: Likewise.
	* g++.dg/other/i386-2.C: Likewise.
	* g++.dg/other/i386-3.C: Likewise.

Co-Authored-By: H.J. Lu <hongjiu.lu@intel.com>
Co-Authored-By: Olga Makhotina <olga.makhotina@intel.com>

From-SVN: r272668

1 files changed, 21 insertions, 1 deletions

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index 096aa3d..a394f87 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -100,6 +100,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_XSAVEC_SET \
   (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
+#define OPTION_MASK_ISA_AVX512VP2INTERSECT_SET OPTION_MASK_ISA_AVX512VP2INTERSECT
 
 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
    as -msse4.2.  */
@@ -240,6 +241,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG
 #define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE
 #define OPTION_MASK_ISA_ENQCMD_UNSET OPTION_MASK_ISA_ENQCMD
+#define OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA_AVX512VP2INTERSECT
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
    as -mno-sse4.1. */
@@ -282,7 +284,8 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AVX512F_UNSET \
   (OPTION_MASK_ISA_AVX512BF16_UNSET \
    | OPTION_MASK_ISA_AVX5124FMAPS_UNSET \
-   | OPTION_MASK_ISA_AVX5124VNNIW_UNSET)
+   | OPTION_MASK_ISA_AVX5124VNNIW_UNSET \
+   | OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET)
 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
   (OPTION_MASK_ISA2_AVX512F_UNSET)
 
@@ -880,6 +883,23 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       return true;
 
+    case OPT_mavx512vp2intersect:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VP2INTERSECT_SET;
+	  opts->x_ix86_isa_flags2_explicit |=
+	    OPTION_MASK_ISA_AVX512VP2INTERSECT_SET;
+	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
+	  opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |=
+	    OPTION_MASK_ISA_AVX512VP2INTERSECT_UNSET;
+	}
+      return true;
+
     case OPT_mfma:
       if (value)
 	{