Merge from trunk revision 5eb9f117a361538834b9740d59219911680717d1.

10 files changed, 232 insertions, 158 deletions

diff --git a/gcc/common/config/aarch64/aarch64-common.cc b/gcc/common/config/aarch64/aarch64-common.cc
index dfda5b8..7fac90d 100644
--- a/gcc/common/config/aarch64/aarch64-common.cc
+++ b/gcc/common/config/aarch64/aarch64-common.cc
@@ -314,8 +314,7 @@ aarch64_option_init_struct (struct gcc_options *opts ATTRIBUTE_UNUSED)
        pop and attribute change (arm_neon headers, lto etc all cause this to
        happen quite frequently).  It is a trade-off between time and space and
        so time won.  */
-    int n_extensions
-      = sizeof (all_extensions) / sizeof (struct aarch64_option_extension);
+    int n_extensions = ARRAY_SIZE (all_extensions);
     qsort (&all_extensions_by_on, n_extensions,
 	   sizeof (struct aarch64_option_extension), opt_ext_cmp);
 }
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 61b1a0f..bbced8a 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -55,43 +55,49 @@ struct __processor_model2
 static inline int
 has_cpu_feature (struct __processor_model *cpu_model,
 		 unsigned int *cpu_features2,
-		 enum processor_features f)
+		 enum processor_features feature)
 {
-  unsigned int i;
+  unsigned index, offset;
+  unsigned f = feature;
+
   if (f < 32)
     {
       /* The first 32 features.  */
-      return cpu_model->__cpu_features[0] & (1U << (f & 31));
+      return cpu_model->__cpu_features[0] & (1U << f);
+    }
+  else
+    {
+      /* The rest of features.  cpu_features2[i] contains features from
+	 (32 + i * 32) to (31 + 32 + i * 32), inclusively.  */
+      f -= 32;
+      index = f / 32;
+      offset = f % 32;
+      return cpu_features2[index] & (1U << offset);
     }
-  /* The rest of features.  cpu_features2[i] contains features from
-     (32 + i * 32) to (31 + 32 + i * 32), inclusively.  */
-  for (i = 0; i < SIZE_OF_CPU_FEATURES; i++)
-    if (f < (32 + 32 + i * 32))
-    return cpu_features2[i] & (1U << ((f - (32 + i * 32)) & 31));
-  gcc_unreachable ();
 }
 
 static inline void
 set_cpu_feature (struct __processor_model *cpu_model,
 		 unsigned int *cpu_features2,
-		 enum processor_features f)
+		 enum processor_features feature)
 {
-  unsigned int i;
+  unsigned index, offset;
+  unsigned f = feature;
+
   if (f < 32)
     {
       /* The first 32 features.  */
-      cpu_model->__cpu_features[0] |= (1U << (f & 31));
-      return;
+      cpu_model->__cpu_features[0] |= (1U << f);
+    }
+  else
+    {
+      /* The rest of features.  cpu_features2[i] contains features from
+	 (32 + i * 32) to (31 + 32 + i * 32), inclusively.  */
+      f -= 32;
+      index = f / 32;
+      offset = f % 32;
+      cpu_features2[index] |= (1U << offset);
     }
-  /* The rest of features.  cpu_features2[i] contains features from
-     (32 + i * 32) to (31 + 32 + i * 32), inclusively.  */
-  for (i = 0; i < SIZE_OF_CPU_FEATURES; i++)
-    if (f < (32 + 32 + i * 32))
-      {
-	cpu_features2[i] |= (1U << ((f - (32 + i * 32)) & 31));
-	return;
-      }
-  gcc_unreachable ();
 }
 
 /* Get the specific type of AMD CPU and return AMD CPU name.  Return
@@ -520,6 +526,39 @@ get_intel_cpu (struct __processor_model *cpu_model,
   return cpu;
 }
 
+/* Get the specific type of ZHAOXIN CPU and return ZHAOXIN CPU name.
+   Return NULL for unknown ZHAOXIN CPU.  */
+
+static inline const char *
+get_zhaoxin_cpu (struct __processor_model *cpu_model,
+		struct __processor_model2 *cpu_model2,
+		unsigned int *cpu_features2)
+{
+  const char *cpu = NULL;
+  unsigned int family = cpu_model2->__cpu_family;
+  unsigned int model = cpu_model2->__cpu_model;
+
+  switch (family)
+    {
+    /* ZHAOXIN family 7h.  */
+    case 0x07:
+      cpu_model->__cpu_type = ZHAOXIN_FAM7H;
+      if (model == 0x3b)
+	{
+	cpu = "lujiazui";
+	CHECK___builtin_cpu_is ("lujiazui");
+	cpu_model->__cpu_features[0] &= ~(1U <<(FEATURE_AVX & 31));
+	cpu_features2[0] &= ~(1U <<((FEATURE_F16C - 32) & 31));
+	cpu_model->__cpu_subtype = ZHAOXIN_FAM7H_LUJIAZUI;
+	}
+      break;
+    default:
+      break;
+    }
+
+  return cpu;
+}
+
 /* ECX and EDX are output of CPUID at level one.  */
 static inline void
 get_available_features (struct __processor_model *cpu_model,
@@ -612,8 +651,6 @@ get_available_features (struct __processor_model *cpu_model,
     set_feature (FEATURE_MOVBE);
   if (ecx & bit_AES)
     set_feature (FEATURE_AES);
-  if (ecx & bit_F16C)
-    set_feature (FEATURE_F16C);
   if (ecx & bit_RDRND)
     set_feature (FEATURE_RDRND);
   if (ecx & bit_XSAVE)
@@ -624,6 +661,8 @@ get_available_features (struct __processor_model *cpu_model,
 	set_feature (FEATURE_AVX);
       if (ecx & bit_FMA)
 	set_feature (FEATURE_FMA);
+      if (ecx & bit_F16C)
+	set_feature (FEATURE_F16C);
     }
 
   /* Get Advanced Features at level 7 (eax = 7, ecx = 0/1). */
@@ -644,6 +683,8 @@ get_available_features (struct __processor_model *cpu_model,
 	    set_feature (FEATURE_AVX2);
 	  if (ecx & bit_VPCLMULQDQ)
 	    set_feature (FEATURE_VPCLMULQDQ);
+	  if (ecx & bit_VAES)
+	    set_feature (FEATURE_VAES);
 	}
       if (ebx & bit_BMI2)
 	set_feature (FEATURE_BMI2);
@@ -666,8 +707,6 @@ get_available_features (struct __processor_model *cpu_model,
 	set_feature (FEATURE_PKU);
       if (ecx & bit_RDPID)
 	set_feature (FEATURE_RDPID);
-      if (ecx & bit_VAES)
-	set_feature (FEATURE_VAES);
       if (ecx & bit_GFNI)
 	set_feature (FEATURE_GFNI);
       if (ecx & bit_MOVDIRI)
@@ -779,11 +818,11 @@ get_available_features (struct __processor_model *cpu_model,
   /* Get Advanced Features at level 0x19 (eax = 0x19).  */
   if (max_cpuid_level >= 0x19)
     {
-      set_feature (FEATURE_AESKLE);
-      __cpuid (19, eax, ebx, ecx, edx);
+      __cpuid (0x19, eax, ebx, ecx, edx);
       /* Check if OS support keylocker.  */
       if (ebx & bit_AESKLE)
 	{
+	  set_feature (FEATURE_AESKLE);
 	  if (ebx & bit_WIDEKL)
 	    set_feature (FEATURE_WIDEKL);
 	  if (has_kl)
@@ -930,8 +969,27 @@ cpu_indicator_init (struct __processor_model *cpu_model,
       get_amd_cpu (cpu_model, cpu_model2, cpu_features2);
       cpu_model->__cpu_vendor = VENDOR_AMD;
     }
-  else if (vendor == signature_CENTAUR_ebx)
+  else if (vendor == signature_CENTAUR_ebx && family < 0x07)
     cpu_model->__cpu_vendor = VENDOR_CENTAUR;
+  else if (vendor == signature_SHANGHAI_ebx
+		|| vendor == signature_CENTAUR_ebx)
+    {
+      /* Adjust model and family for ZHAOXIN CPUS.  */
+      if (family == 0x07)
+	{
+	  model += extended_model;
+	}
+
+      cpu_model2->__cpu_family = family;
+      cpu_model2->__cpu_model = model;
+
+      /* Find available features.  */
+      get_available_features (cpu_model, cpu_model2, cpu_features2,
+				  ecx, edx);
+      /* Get CPU type.  */
+      get_zhaoxin_cpu (cpu_model, cpu_model2,cpu_features2);
+      cpu_model->__cpu_vendor = VENDOR_ZHAOXIN;
+    }
   else if (vendor == signature_CYRIX_ebx)
     cpu_model->__cpu_vendor = VENDOR_CYRIX;
   else if (vendor == signature_NSC_ebx)
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 449df63..c0c2ad7 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -315,13 +315,12 @@ along with GCC; see the file COPYING3.  If not see
    | OPTION_MASK_ISA_SSE_UNSET)
 
 #define OPTION_MASK_ISA2_AVX512F_UNSET \
-  (OPTION_MASK_ISA2_AVX512BF16_UNSET \
+  (OPTION_MASK_ISA2_AVX512BW_UNSET \
    | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
    | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
-   | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
-   | OPTION_MASK_ISA2_AVX512FP16_UNSET)
+   | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
-  (OPTION_MASK_ISA2_AVX512F_UNSET)
+  OPTION_MASK_ISA2_SSE_UNSET
 #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET
 #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
 #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
@@ -1817,6 +1816,7 @@ const char *const processor_names[] =
   "alderlake",
   "rocketlake",
   "intel",
+  "lujiazui",
   "geode",
   "k6",
   "athlon",
@@ -1995,6 +1995,13 @@ const pta processor_alias_table[] =
   {"nano-x4", PROCESSOR_K8, CPU_K8,
     PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
       | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
+  {"lujiazui", PROCESSOR_LUJIAZUI, CPU_LUJIAZUI,
+    PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+	| PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
+	| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_BMI | PTA_BMI2
+	| PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
+	| PTA_RDRND | PTA_MOVBE | PTA_ADX | PTA_RDSEED | PTA_POPCNT,
+	M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), P_NONE},
   {"k8", PROCESSOR_K8, CPU_K8,
     PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
       | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index 3f6d201..643fbd9 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -29,6 +29,7 @@ enum processor_vendor
 {
   VENDOR_INTEL = 1,
   VENDOR_AMD,
+  VENDOR_ZHAOXIN,
   VENDOR_OTHER,
   VENDOR_CENTAUR,
   VENDOR_CYRIX,
@@ -56,6 +57,7 @@ enum processor_types
   INTEL_GOLDMONT_PLUS,
   INTEL_TREMONT,
   AMDFAM19H,
+  ZHAOXIN_FAM7H,
   CPU_TYPE_MAX,
   BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
 };
@@ -89,6 +91,7 @@ enum processor_subtypes
   INTEL_COREI7_ALDERLAKE,
   AMDFAM19H_ZNVER3,
   INTEL_COREI7_ROCKETLAKE,
+  ZHAOXIN_FAM7H_LUJIAZUI,
   CPU_SUBTYPE_MAX
 };
 
diff --git a/gcc/common/config/loongarch/loongarch-common.cc b/gcc/common/config/loongarch/loongarch-common.cc
new file mode 100644
index 0000000..f8b4660
--- /dev/null
+++ b/gcc/common/config/loongarch/loongarch-common.cc
@@ -0,0 +1,41 @@
+/* Common hooks for LoongArch.
+   Copyright (C) 2021-2022 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+#include "opts.h"
+#include "flags.h"
+#include "diagnostic-core.h"
+
+#undef	TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE loongarch_option_optimization_table
+
+/* Set default optimization options.  */
+static const struct default_options loongarch_option_optimization_table[] =
+{
+  { OPT_LEVELS_ALL, OPT_fasynchronous_unwind_tables, NULL, 1 },
+  { OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+  { OPT_LEVELS_NONE, 0, NULL, 0 }
+};
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index a904893..0e5be2c 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -165,6 +165,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zksh",  ISA_SPEC_CLASS_NONE, 1, 0},
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0},
+
+  {"zk",    ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zkn",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zks",   ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zve32x", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zve32f", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zve32d", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -189,6 +197,16 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
 
+/* Combine extensions defined in this table  */
+static const struct riscv_ext_version riscv_combine_info[] =
+{
+  {"zk",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zkn",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zks",  ISA_SPEC_CLASS_NONE, 1, 0},
+  /* Terminate the list.  */
+  {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
+};
+
 static const riscv_cpu_info riscv_cpu_tables[] =
 {
 #define RISCV_CORE(CORE_NAME, ARCH, TUNE) \
@@ -580,7 +598,7 @@ riscv_subset_list::lookup (const char *subset, int major_version,
 static const char *
 riscv_supported_std_ext (void)
 {
-  return "mafdqlcbjktpvn";
+  return "mafdqlcbkjtpvn";
 }
 
 /* Parsing subset version.
@@ -813,6 +831,50 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
     }
 }
 
+/* Check any combine extensions for EXT.  */
+void
+riscv_subset_list::handle_combine_ext ()
+{
+  const riscv_ext_version *combine_info;
+  const riscv_implied_info_t *implied_info;
+  bool is_combined = false;
+
+  for (combine_info = &riscv_combine_info[0]; combine_info->name;
+       ++combine_info)
+    {
+      /* Skip if combine extensions are present */
+      if (lookup (combine_info->name))
+	continue;
+
+      /* Find all extensions of the combine extension   */
+      for (implied_info = &riscv_implied_info[0]; implied_info->ext;
+	   ++implied_info)
+	{
+	  /* Skip if implied extension don't match combine extension */
+	  if (strcmp (combine_info->name, implied_info->ext) != 0)
+	    continue;
+
+	  if (lookup (implied_info->implied_ext))
+	    is_combined = true;
+	  else
+	    {
+	      is_combined = false;
+	      break;
+	    }
+	}
+
+      /* Add combine extensions */
+      if (is_combined)
+	{
+	  if (lookup (combine_info->name) == NULL)
+	    {
+	      add (combine_info->name, combine_info->major_version,
+		   combine_info->minor_version, false, true);
+	    }
+	}
+    }
+}
+
 /* Parsing function for multi-letter extensions.
 
    Return Value:
@@ -992,6 +1054,8 @@ riscv_subset_list::parse (const char *arch, location_t loc)
       subset_list->handle_implied_ext (itr);
     }
 
+  subset_list->handle_combine_ext ();
+
   return subset_list;
 
 fail:
@@ -1050,22 +1114,26 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zksh",   &gcc_options::x_riscv_zk_subext, MASK_ZKSH},
   {"zkt",    &gcc_options::x_riscv_zk_subext, MASK_ZKT},
 
+  {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ},
+  {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
+  {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
+
   {"zve32x",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve32f",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve64x",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve64f",   &gcc_options::x_target_flags, MASK_VECTOR},
   {"zve64d",   &gcc_options::x_target_flags, MASK_VECTOR},
 
-  /* We don't need to put complete EEW/EEW_FP info here, due to the
+  /* We don't need to put complete ELEN/ELEN_FP info here, due to the
      implication relation of vector extension.
-     e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_EEW_FP_64,
-     MASK_VECTOR_EEW_FP_32, MASK_VECTOR_EEW_64 and MASK_VECTOR_EEW_32
+     e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_ELEN_FP_64,
+     MASK_VECTOR_ELEN_FP_32, MASK_VECTOR_ELEN_64 and MASK_VECTOR_ELEN_32
      due to the extension implication.  */
-  {"zve32x",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_32},
-  {"zve32f",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
-  {"zve64x",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_64},
-  {"zve64f",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
-  {"zve64d",   &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_64},
+  {"zve32x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32},
+  {"zve32f",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
+  {"zve64x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
+  {"zve64f",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
+  {"zve64d",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64},
 
   {"zvl32b",    &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
   {"zvl64b",    &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
diff --git a/gcc/common/config/rs6000/rs6000-common.cc b/gcc/common/config/rs6000/rs6000-common.cc
index 97dff3a..8e393d0 100644
--- a/gcc/common/config/rs6000/rs6000-common.cc
+++ b/gcc/common/config/rs6000/rs6000-common.cc
@@ -227,6 +227,16 @@ rs6000_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
 	}
       break;
 
+    case OPT_mabi_ibmlongdouble:
+    case OPT_mabi_ieeelongdouble:
+      if (opts->x_rs6000_long_double_type_size == 64)
+	{
+	  error_at (loc, "option %<%s%> requires %<-mlong-double-128%>",
+		    decoded->orig_option_with_args_text);
+	  return true;
+	}
+      break;
+
     case OPT_mrecip:
       opts->x_rs6000_recip_name = (value) ? "default" : "none";
       break;
diff --git a/gcc/common/config/s390/s390-common.cc b/gcc/common/config/s390/s390-common.cc
index caec2f1..72a5ef4 100644
--- a/gcc/common/config/s390/s390-common.cc
+++ b/gcc/common/config/s390/s390-common.cc
@@ -50,10 +50,10 @@ EXPORTED_CONST int processor_flags_table[] =
     /* z15 */    PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
 		 | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX
 		 | PF_Z13 | PF_VX | PF_VXE | PF_Z14 | PF_VXE2 | PF_Z15,
-    /* arch14 */ PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
+    /* z16 */    PF_IEEE_FLOAT | PF_ZARCH | PF_LONG_DISPLACEMENT
 		 | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 | PF_ZEC12 | PF_TX
 		 | PF_Z13 | PF_VX | PF_VXE | PF_Z14 | PF_VXE2 | PF_Z15
-		 | PF_NNPA | PF_ARCH14
+		 | PF_NNPA | PF_Z16
   };
 
 /* Change optimizations to be performed, depending on the
diff --git a/gcc/common/config/tilegx/tilegx-common.cc b/gcc/common/config/tilegx/tilegx-common.cc
deleted file mode 100644
index 3d33b7b..0000000
--- a/gcc/common/config/tilegx/tilegx-common.cc
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Common hooks for TILE-Gx.
-   Copyright (C) 2011-2022 Free Software Foundation, Inc.
-   Contributed by Walter Lee (walt@tilera.com)
-
-   This file is part of GCC.
-
-   GCC is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published
-   by the Free Software Foundation; either version 3, or (at your
-   option) any later version.
-
-   GCC is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GCC; see the file COPYING3.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#include "config.h"
-#include "system.h"
-#include "coretypes.h"
-#include "diagnostic-core.h"
-#include "tm.h"
-#include "common/common-target.h"
-#include "common/common-target-def.h"
-#include "opts.h"
-#include "flags.h"
-
-static const struct default_options tilegx_option_optimization_table[] = {
-  /* Scheduling and bundling are super important for our architecture, so
-     enable them at -O1. */
-  {OPT_LEVELS_1_PLUS, OPT_fschedule_insns, NULL, 1},
-  {OPT_LEVELS_1_PLUS, OPT_fschedule_insns2, NULL, 1},
-  {OPT_LEVELS_NONE, 0, NULL, 0}
-};
-
-
-static void
-tilegx_option_init_struct (struct gcc_options *opts)
-{
-  opts->x_flag_asynchronous_unwind_tables = 1;
-}
-
-
-#undef  TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS \
-  (TARGET_DEFAULT		    \
-   | TARGET_ENDIAN_DEFAULT)
-
-#undef  TARGET_OPTION_OPTIMIZATION_TABLE
-#define TARGET_OPTION_OPTIMIZATION_TABLE tilegx_option_optimization_table
-
-#undef  TARGET_OPTION_INIT_STRUCT
-#define TARGET_OPTION_INIT_STRUCT tilegx_option_init_struct
-
-struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/common/config/tilepro/tilepro-common.cc b/gcc/common/config/tilepro/tilepro-common.cc
deleted file mode 100644
index 8e09736..0000000
--- a/gcc/common/config/tilepro/tilepro-common.cc
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Common hooks for TILEPro.
-   Copyright (C) 2011-2022 Free Software Foundation, Inc.
-   Contributed by Walter Lee (walt@tilera.com)
-
-   This file is part of GCC.
-
-   GCC is free software; you can redistribute it and/or modify it
-   under the terms of the GNU General Public License as published
-   by the Free Software Foundation; either version 3, or (at your
-   option) any later version.
-
-   GCC is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GCC; see the file COPYING3.  If not see
-   <http://www.gnu.org/licenses/>.  */
-
-#include "config.h"
-#include "system.h"
-#include "coretypes.h"
-#include "diagnostic-core.h"
-#include "tm.h"
-#include "common/common-target.h"
-#include "common/common-target-def.h"
-#include "opts.h"
-#include "flags.h"
-
-static const struct default_options tilepro_option_optimization_table[] = {
-  /* Scheduling and bundling are super important for our architecture, so
-     enable them at -O1. */
-  {OPT_LEVELS_1_PLUS, OPT_fschedule_insns, NULL, 1},
-  {OPT_LEVELS_1_PLUS, OPT_fschedule_insns2, NULL, 1},
-  {OPT_LEVELS_NONE, 0, NULL, 0}
-};
-
-
-static void
-tilepro_option_init_struct (struct gcc_options *opts)
-{
-  opts->x_flag_asynchronous_unwind_tables = 1;
-}
-
-
-
-#undef  TARGET_OPTION_OPTIMIZATION_TABLE
-#define TARGET_OPTION_OPTIMIZATION_TABLE tilepro_option_optimization_table
-
-#undef  TARGET_OPTION_INIT_STRUCT
-#define TARGET_OPTION_INIT_STRUCT tilepro_option_init_struct
-
-struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;