Support Intel MOVRS

gcc/ChangeLog:

	* builtins.cc (expand_builtin_prefetch): Expand for
	prefetchrst2.
	* common/config/i386/cpuinfo.h (get_available_features): Detect movrs.
	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_MOVRS_SET): New.
	(OPTION_MASK_ISA2_MOVRS_UNSET): Ditto.
	(ix86_handle_option): Handle -mmovrs.
	* common/config/i386/i386-cpuinfo.h
	(enum processor_features): Add FEATURE_MOVRS.
	* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for movrs.
	* config.gcc: Add movrsintrin.h
	* config/i386/cpuid.h (bit_MOVRS): New.
	* config/i386/i386-builtin-types.def:
	Add DEF_FUNCTION_TYPE (CHAR, PCCHAR), (SHORT, PCSHORT), (INT, PCINT),
	(INT64, PCINT64).
	* config/i386/i386-builtin.def (BDESC): Add new builtins.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Add
	__MOVRS__.
	* config/i386/i386-expand.cc (ix86_expand_special_args_builtin): Define
	__MOVRS__.
	* config/i386/i386-isa.def (MOVRS): Add DEF_PTA(MOVRS)
	* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
	Handle movrs.
	* config/i386/i386.md (movrs<mode>): New.
	* config/i386/i386.opt: Add option -mmovrs.
	* config/i386/i386.opt.urls: Regenerated.
	* config/i386/immintrin.h: Include movrsintrin.h
	* config/i386/sse.md (unspecv): Add UNSPEC_VMOVRS.
	(VI1248_AVX10_2): New.
	(avx10_2_movrs_vmovrs<ssemodesuffix><mode><mask_name>): New define_insn.
	* config/i386/xmmintrin.h: Add prefetchrst2.
	* doc/extend.texi: Document movrs.
	* doc/invoke.texi: Document -mmovrs.
	* doc/rtl.texi: Document extension of prefetchrst2.
	* doc/sourcebuild.texi: Document target movrs.
	* config/i386/movrsintrin.h: New.

gcc/testsuite/ChangeLog:

	* g++.dg/other/i386-2.C: Add -mmovrs.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.c-torture/execute/builtin-prefetch-1.c: Expand rws.
	* gcc.dg/builtin-prefetch-1.c: Ditto.
	* gcc.target/i386/avx-1.c: Ditto.
	* gcc.target/i386/avx-2.c: Ditto.
	* gcc.target/i386/funcspec-56.inc: Add new target attribute.
	* gcc.target/i386/sse-12.c: Add -mmovrs.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Add movrs.
	* gcc.target/i386/sse-23.c: Ditto
	* gcc.target/i386/avx10_2-512-movrs-1.c: New test.
	* gcc.target/i386/avx10_2-movrs-1.c: Ditto.
	* gcc.target/i386/movrs-1.c: Ditto.

Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>

4 files changed, 20 insertions, 0 deletions

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index b128c31..14af8bf 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -918,6 +918,8 @@ get_available_features (struct __processor_model *cpu_model,
 	    set_feature (FEATURE_RAOINT);
 	  if (edx & bit_USER_MSR)
 	    set_feature (FEATURE_USER_MSR);
+	  if (eax & bit_MOVRS)
+	    set_feature (FEATURE_MOVRS);
 	  if (avx_usable)
 	    {
 	      if (eax & bit_AVXVNNI)
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 771bde2..86cacf5 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -136,6 +136,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_TRANSPOSE)
 #define OPTION_MASK_ISA2_AMX_FP8_SET \
   (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP8)
+#define OPTION_MASK_ISA2_MOVRS_SET OPTION_MASK_ISA2_MOVRS
 
 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
    as -msse4.2.  */
@@ -334,6 +335,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_AMX_TF32_UNSET OPTION_MASK_ISA2_AMX_TF32
 #define OPTION_MASK_ISA2_AMX_TRANSPOSE_UNSET OPTION_MASK_ISA2_AMX_TRANSPOSE
 #define OPTION_MASK_ISA2_AMX_FP8_UNSET OPTION_MASK_ISA2_AMX_FP8
+#define OPTION_MASK_ISA2_MOVRS_UNSET OPTION_MASK_ISA2_MOVRS
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
    as -mno-sse4.1. */
@@ -1480,6 +1482,20 @@ ix86_handle_option (struct gcc_options *opts,
 	}
       return true;
 
+    case OPT_mmovrs:
+      if (value)
+	{
+	  opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVRS_SET;
+	  opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVRS_SET;
+	}
+      else
+	{
+	  opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVRS_UNSET;
+	  opts->x_ix86_isa_flags2_explicit |=
+	    OPTION_MASK_ISA2_MOVRS_UNSET;
+	}
+      return true;
+
     case OPT_mfma:
       if (value)
 	{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index 68d6325..f170aaf 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -273,6 +273,7 @@ enum processor_features
   FEATURE_AMX_TF32,
   FEATURE_AMX_TRANSPOSE,
   FEATURE_AMX_FP8, 
+  FEATURE_MOVRS,
   CPU_FEATURE_MAX
 };
 
diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index ccd0d19..d454173 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -195,4 +195,5 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("amx-transpose", FEATURE_AMX_TRANSPOSE,
 			P_NONE, "-mamx-transpose")
   ISA_NAMES_TABLE_ENTRY("amx-fp8", FEATURE_AMX_FP8, P_NONE, "-mamx-fp8")
+  ISA_NAMES_TABLE_ENTRY("movrs", FEATURE_MOVRS, P_NONE, "-mmovrs")
 ISA_NAMES_TABLE_END