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| author | Richard Earnshaw <rearnsha@arm.com> | 2003-10-17 10:58:17 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2003-10-17 10:58:17 +0000 |
| commit | defc0463c448ba444136bee65ee482644eb7fd66 (patch) | |
| tree | d402bff7289bb069a9367b802d647c14c1d1d00f /gcc/combine.c | |
| parent | 38b2a60531f0da9ee440c82248774bf53596edf0 (diff) | |
| download | gcc-defc0463c448ba444136bee65ee482644eb7fd66.zip gcc-defc0463c448ba444136bee65ee482644eb7fd66.tar.gz gcc-defc0463c448ba444136bee65ee482644eb7fd66.tar.bz2 | |
arm-modes.def (CC_Nmode): New condition code mode.
* arm-modes.def (CC_Nmode): New condition code mode.
* arm.c (thumb_condition_code): Delete.
(arm_select_cc_mode): Handle single-bit test for Thumb.
(arm_print_operand, cases 'd' and 'D'): Don't special case the
condition code logic for Thumb.
(get_arm_condition_code): Handle CC_Nmode.
(thumb_cbrch_target_operand): New function.
* arm.h (PREDICATE_CODES): Add thumb_cbrch_target_operand.
* arm-protos.h (thumb_cbrch_target_operand): Add prototype.
* arm.md: Add Thumb split patterns for zero_extract and
sign_extract.
(tbit_cbranch, andsi3_cbranch_scratch, andsi3_cbranch)
(orrsi3_cbranch_scratch, orrsi3_cbranch, xorsi3_cbranch_scratch)
(xorsi3_cbranch, addsi3_cbranch, addsi3_cbranch_scratch)
(subsi3_cbranch, subsi3_cbranch_scratch): New Thumb patterns.
(cbranchne_decr1): Re-work to use CC_Nmode.
* arm.c (thumb_expand_epilogue): Add clobbers of registers restored
by the return instruction. Add a use of the link register if it
wasn't stored.
From-SVN: r72595
Diffstat (limited to 'gcc/combine.c')
0 files changed, 0 insertions, 0 deletions