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author | Jakub Jelinek <jakub@redhat.com> | 2022-06-04 10:36:24 +0200 |
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committer | Jakub Jelinek <jakub@redhat.com> | 2022-06-04 10:36:24 +0200 |
commit | 53718316afa45eb0d1c236fbbf2fc0959b08510f (patch) | |
tree | 021c2e48ff76804ed24353a4cc568357139d1bff /gcc/calls.cc | |
parent | 58b67140de7685de25b2f5775b5735f9c491b058 (diff) | |
download | gcc-53718316afa45eb0d1c236fbbf2fc0959b08510f.zip gcc-53718316afa45eb0d1c236fbbf2fc0959b08510f.tar.gz gcc-53718316afa45eb0d1c236fbbf2fc0959b08510f.tar.bz2 |
i386: Fix up *_doubleword_mask [PR105825]
My PR105778 patch apparently broke the following testcase.
If the mask has the top relevant bit clear (i.e. we know we are shifting
by 0 to wordsize bits - 1) but doesn't have all the bits below it set,
we emit andsi3 before the shift sequence. When the pattern had :SI
for that operand, that was just fine, but now that it can be also HImode
or for -m64 DImode, we either can use a lowpart or paradoxical subreg to
SImode as the following patch, or we use a HImode or DImode AND.
This patch does the latter.
2022-06-04 Jakub Jelinek <jakub@redhat.com>
PR target/105825
* config/i386/i386.md (*ashl<dwi>3_doubleword_mask,
*<insn><dwi>3_doubleword_mask): If top bit of mask is clear, but lower
bits of mask aren't all set, use operands[2] mode for the AND
operation instead of always SImode.
* gcc.dg/pr105825.c: New test.
Diffstat (limited to 'gcc/calls.cc')
0 files changed, 0 insertions, 0 deletions